TDA6650TT Datasheet, PDF (48/55 Pages) NXP Semiconductors – 5 V mixer/oscillator and low noise PLL synthesizer for hybrid terrestrial tuner (digital and analog)

Philips Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
Product specification
TDA6650TT;
TDA6651TT
14 APPLICATION AND TEST INFORMATION
14.1 Tuning amplifier
The tuning amplifier is capable of driving the varicap
voltage without an external transistor. The tuning voltage
output must be connected to an external load of 15 kΩ
which is connected to the tuning voltage supply rail. The
loop filter design depends on the oscillator characteristics
and the selected reference frequency as well as the
required PLL loop bandwidth.
Applications with the TDA6650TT; TDA6651TT have a
large loop bandwidth, in the order of a few tens of kHz. The
calculation of the loop filter elements has to be done for
each application, it depends on the reference frequency
and charge pump current. A simulation of the loop can
easily be done using the SIMPATA software from Philips.
14.2 Crystal oscillator
The TDA6650TT; TDA6651TT needs to be used with a
4 MHz crystal in series with a capacitor with a typical value
of 18 pF, connected between pin XTAL1 and pin XTAL2.
Philips crystal 4322 143 04093 is recommended. When
choosing a crystal, take care to select a crystal able to
withstand the drive level of the TDA6650TT; TDA6651TT
without suffering from accelerated ageing. For optimum
performances, it is highly recommended to connect the
4 MHz crystal without any serial resistance.
The crystal oscillator of the TDA6650TT; TDA6651TT
should not be driven (forced) from an external signal.
Do not use the signal on pins XTAL1 or XTAL2, or the
signal present on the crystal, to drive an external IC or for
any other use as this may dramatically degrade the phase
noise performance of the TDA6650TT; TDA6651TT.
14.3 Examples of I²C-bus program sequences
Tables 16 to 23 show various sequences where:
S = START
A = acknowledge
P = STOP.
The following conditions apply:
LO frequency is 800 MHz
f_comp = 166.666 kHz
N = 4800
BS3 output port is on and all other ports are off: thus the
high band is selected
Charge pump current I_CP = 280 µA
Normal mode, with XTOUT buffer on
I_AGC = 220 nA
AGC take-over point is set to 112 dBµV (p-p)
Address selection is adjusted to make address C2 valid.
To fully program the device, either sequence of Table 16
or 17 can be used, while other arrangements of the bytes
are also possible.
Table 16 Complete sequence 1
START
S
ADDRESS
BYTE
C2
A
DIVIDER
BYTE 1
12
A
DIVIDER
BYTE 2
C0
A
CONTROL
BYTE 1⁽¹⁾
CA
A
CONTROL
BYTE 2
A4
A
CONTROL
BYTE 1⁽²⁾
84
A
STOP
P
Notes
1. Control byte 1 with bit T/A = 1, to program test bits T2, T1 and T0 and reference divider ratio bits R2, R1 and R0.
2. Control byte 1 with bit T/A = 0, to program AGC time constant bit ATC and AGC take-over point bits AL2, AL1
and AL0.
Table 17 Complete sequence 2
START
S
ADDRESS
BYTE
C2
A
CONTROL
BYTE 1⁽¹⁾
CA
A
CONTROL
BYTE 2
A4
A
DIVIDER
BYTE 1
12
A
DIVIDER
BYTE 2
C0
A
CONTROL
BYTE 1⁽²⁾
84
A
STOP
P
Notes
1. Control byte 1 with bit T/A = 1, to program test bits T2, T1 and T0 and reference divider ratio bits R2, R1 and R0.
2. Control byte 1 with bit T/A = 0, to program AGC time constant bit ATC and AGC take-over point bits AL2, AL1
and AL0.
2004 Mar 22
48