TDA6650TT Datasheet, PDF (14/55 Pages) NXP Semiconductors – 5 V mixer/oscillator and low noise PLL synthesizer for hybrid terrestrial tuner (digital and analog)

Philips Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
Product specification
TDA6650TT;
TDA6651TT
8.2 Read mode; R/W = 1
Data can be read from the device by setting the R/W bit
to 1 (see Table 12). After the device address has been
recognized, the device generates an acknowledge pulse
and the first data byte (status byte) is transferred on the
SDA line (MSB first). Data is valid on the SDA line during
a HIGH level of the SCL clock signal.
A second data byte can be read from the device if the
microcontroller generates an acknowledge on the SDA
line (master acknowledge). End of transmission will occur
if no master acknowledge occurs. The device will then
release the data line to allow the microcontroller to
generate a STOP condition.
Table 12 I²C-bus read data format
NAME
Address byte
Status byte
BYTE
MSB⁽¹⁾
1
1
1
2
POR
FL
Note
1. MSB is transmitted first.
0
ALBC
BIT
0
0
MA1
1
AGC
A2
Table 13 Description of read data format bits
BIT
A
POR
FL
ALBC
AGC
A2, A1, A0
DESCRIPTION
acknowledge bit
Power-on reset flag
POR = 0, normal operation
POR = 1, Power-on reset
in-lock flag
FL = 0, not locked
FL = 1, the PLL is locked
automatic loop bandwidth control flag
ALBC = 0, no automatic loop bandwidth control
ALBC = 1, automatic loop bandwidth control selected
internal AGC flag
AGC = 0 when internal AGC is active (V_AGC < V_RML)
AGC = 1 when internal AGC is not active (V_AGC > V_RMH)
digital outputs of the 5-level ADC; see Table 14
MA0
A1
ACK
LSB
R/W = 1 A
A0
−
2004 Mar 22
14