TDA6650TT Datasheet, PDF (11/55 Pages) NXP Semiconductors – 5 V mixer/oscillator and low noise PLL synthesizer for hybrid terrestrial tuner (digital and analog)

Philips Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
Product specification
TDA6650TT;
TDA6651TT
8.1.2 XTOUT OUTPUT BUFFER AND MODE SETTING
The crystal frequency can be sent to pin XTOUT and used
in the application, for example to drive the clock input of a
digital demodulator, saving a quartz crystal in the bill of
material. To output f_xtal, it is necessary to set T[2:0] to 001.
If the output signal on this pin is not used, it is
recommended to disable it, by setting T[2:0] to 000. This
pin is also used to output ¹/₂f_div and f_comp in a test mode.
At Power-on, the XTOUT output buffer is set to on,
supplying the f_xtal signal. The relation between the signal
on pin XTOUT and the setting of theT[2:0] bits is given in
Table 6.
Table 6 XTOUT buffer status and test modes
T2
T1
T0
PIN XTOUT
MODE
0
0
0
disabled
normal mode with XTOUT buffer off
0
0
1
f_xtal (4 MHz)
normal mode with XTOUT buffer on
0
1
0
1_/2fdiv
charge pump off
0
1
1
f_xtal (4 MHz)
switch ALBC on or off (note 1)
1
0
0
f_comp
test mode
1
0
1
1_/2fdiv
test mode
1
1
0
f_xtal (4 MHz)
charge pump sinking current (note 2)
1
1
1
disabled
charge pump sourcing current
Notes
1. Automatic Loop Bandwidth Control (ALBC) is disabled at Power-on reset. After Power-on reset this feature is
enabled by setting T[2:0] = 011. To disable again the ALBC, set T[2:0] = 011 again. This test mode acts like a toggle
switch, which means each time it is set the status of the ALBC changes. To toggle the ALBC, two consecutive Control
byte 1s (CB1), should be sent: one byte with T[2:0] = 011 indicating that ALBC will be switched on or off and one byte
programming the test mode to be selected (see Table 23, example of I²C-bus sequence).
2. This is the default mode at Power-on reset. This mode disables the tuning voltage.
8.1.3 STEP FREQUENCY SETTING
The step frequency is set by three bits, giving five steps to cope with different application requirements.
The reference divider ratio is automatically set depending on bits R2, R1 and R0. The phase detector works at either
4, 2 or 1 MHz.
Table 7 shows the step frequencies and corresponding reference divider ratios. When the value of bits R2, R1 and R0
are changed, it is necessary to re-send the data bytes DB1 and DB2.
Table 7 Reference divider ratio select bits
R2
R1
R0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
REFERENCE
DIVIDER RATIO
2
1
1
4
1
−
−
−
FREQUENCY
COMPARISON
2 MHz
4 MHz
4 MHz
1 MHz
4 MHz
−
−
−
FREQUENCY STEP
62.5 kHz
142.86 kHz
166.67 kHz
50 kHz
125 kHz
reserved
reserved
reserved
2004 Mar 22
11