TDA6650TT Datasheet, PDF (8/55 Pages) NXP Semiconductors – 5 V mixer/oscillator and low noise PLL synthesizer for hybrid terrestrial tuner (digital and analog)

Philips Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
Product specification
TDA6650TT;
TDA6651TT
It is possible to drive the clock input of a digital
demodulation IC from pin XTOUT with the 4 MHz signal
from the crystal oscillator. This output is also used to
output ¹/₂f_div and f_comp signals in a specific test mode (see
Table 6). It is possible to switch off this output, which is
recommended when it is not used.
For test and alignment purposes, it is also possible to
release the tuning voltage output by selecting the sinking
mode (see Table 6), and by applying an external voltage
on pin VT.
In addition to the BS1 and BS2 output ports that are used
for the band selection, there are three general purpose
ports BS3, BS4 and BS5. All five ports are PMOS
open-drain type, each with 15 mA drive capability. The
connection for port BS5 and the ADC input is combined on
one pin. It is not possible to use the ADC if port BS5 is
used.
The AGC detector compares the level at the IF amplifier
output to a reference level which is selected from
6 different levels via the I²C-bus. The time constant of the
AGC can be selected via the I²C-bus to cope with normal
operation as well as with search operation.
When the output level on pin AGC is higher than the
threshold V_RMH, then bit AGC = 1. When the output level
on pin AGC is lower than the threshold V_RML, then
bit AGC = 0. Between these two thresholds, bit AGC is not
defined. The status of the AGC bit can be read via the
I²C-bus according to the read mode as described in
Table 12.
7.2 I²C-bus voltage
The I²C-bus lines SCL and SDA can be connected to an
I²C-bus system tied to 2.5, 3.3 or 5 V. The choice of the
bus input threshold voltages is made with pin BVS that can
be left open-circuit, connected to the supply voltage or to
ground (see Table 2).
Table 2 I²C-bus voltage selection
PIN BVS
BUS
CONNECTION VOLTAGE
LOGIC LEVEL
LOW
HIGH
To ground
2.5 V 0 to 0.75 V 1.75 to 5.5 V
Open-circuit
3.3 V 0 to 1.0 V 2.3 to 5.5 V
To V_CC
5V
0 to 1.5 V 3.0 to 5.5 V
7.3 Phase noise, I²C-bus traffic and crosstalk
While the TDA6650TT; TDA6651TT is dedicated for hybrid
terrestrial applications, the low noise PLL will clean up the
noise spectrum of the VCOs close to the carrier to reach
noise levels at 1 kHz offset from the carrier compatible with
e.g. DVB-T reception.
Linked to this noise improvement, some disturbances may
become visible while they were not visible because they
were hidden into the noise in analog dedicated
applications and circuits.
This is especially true for disturbances coming from the
I²C-bus traffic, whatever this traffic is intended for the
MOPLL or for another slave on the bus.
To avoid this I²C-bus crosstalk and be able to have a clean
noise spectrum, it is necessary to use a bus gate that
enables the signal on the bus to drive the MOPLL only
when the communication is intended for the tuner part
(such a kind of I²C-bus gate is included into the Philips
terrestrial channel decoders), and to avoid unnecessary
repeated sending of the same information.
8 I²C-BUS PROTOCOL
The TDA6650TT; TDA6651TT is controlled via the
two-wire I²C-bus. For programming, there is one device
address (7 bits) and the R/W bit for selecting read or write
mode. To be able to have more than one MOPLL in an
I²C-bus system, one of four possible addresses is selected
depending on the voltage applied to address selection
pin AS (see Table 5).
The TDA6650TT; TDA6651TT fulfils the fast mode
I²C-bus, according to the Philips I²C-bus specification (see
Chapter 20), except for the timing as described in Fig.4.
The I²C-bus interface is designed in such a way that the
pins SCL and SDA can be connected to 5, 3.3 or to 2.5 V
pulled-up I²C-bus lines, depending on the voltage applied
to pin BVS (see Table 2).
2004 Mar 22
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