83C145 Datasheet, PDF (9/40 Pages) NXP Semiconductors – Microcontrollers for TV and video MTV

Philips Semiconductors
Microcontrollers for TV and video (MTV)
Product specification
83C145; 83C845
83C055; 87C055
10 6-BIT PWM DACS
Figure 3 shows the 6-bit PWM DAC logic circuit, consisting
of 8 PWMn modules.
The basic MCU clock is divided by 4 to get a waveform that
clocks a 14-bit counter which is common to all the PWMs
(including the 14-bit PWM). This divided clock is hereafter
called the PWM clock.
As illustrated in Fig.3, the lower-precision (6-bit) PWMs
use the least significant part of the 14-bit counter.
Figure 4 shows the circuit diagram of a 6-bit PWM module.
Each PWM module has a Special Function Register
PWMn; n = 0 to 7. The register format is shown in Table 6.
10.1 PWM DAC operation
Value field PVn5 to PVn0 of each PWMn register
(n = 0 to 7) is compared to the 6 LSBs of the common
counter (14-bit counter).
When the value matches, the output flip-flop is cleared, so
that the output pin is driven LOW.
When the value rolls over to zero, the output flip-flop is set,
so that the output pin is released. Thus the output
waveform has a fixed period of 64 PWM clock cycles; its
duty cycle is determined by contents of PWMn.5 to
PWMn.0 (PVn5 to PVn0).
Three of the nine total PWM modules (8 PWMn and the
14-bit PWM DAC) operate as previously described; for
three others, both the rising and falling edges of the output
are delayed by one PWM clock; for the remaining three,
both edges are delayed by two PWM clocks. This feature
reduces the radio-frequency emission that would
otherwise occur when the counter rolled over to zero and
all nine open-drain outputs were released.
10.2 Special Function Register PWMn (n = 0 to 7)
Table 6 Special Function Register PWMn (n = 0 to 7; addresses D4H to DFH)
7
6
5
4
3
2
PWnE
−
PVn5
PVn4
PVn3
PVn2
1
PVn1
Table 7 Description of PWMn bits
BIT
7
6
5 to 0
SYMBOL
DESCRIPTION
PWnE PWM module enable bit. If for a particular PWM block (n) the bit:
PWnE = 1, then the block is active and controls its assigned port pin.
PWnE = 0, the corresponding port pin is controlled by the port.
−
Reserved.
PVn5 to PVn0 Value field for PWMn register.
0
PVn0
1996 Mar 22
9