83C145 Datasheet, PDF (29/40 Pages) NXP Semiconductors – Microcontrollers for TV and video MTV

Philips Semiconductors
Microcontrollers for TV and video (MTV)
Product specification
83C145; 83C845
83C055; 87C055
14.5 EPROM Programming and Verification
V_DD = 5 V ±10%; V_SS = 0 V; T_amb = 21 to 27 °C.
SYMBOL
1/t_CLCL
t_AVGL(1)
t_GHAX
t_DVGL
t_GHDX
t_SHGL
t_GHSL
t_GLGH
t_AVQV(1)
t_GHGL
t_SYNL
t_SYNH
t_MASEL
t_HAHLD
t_HASET
t_ADSTA
PARAMETER
Oscillator/clock frequency
Address setup to P0.1 (PROG) LOW
Address hold after P0.1 (PROG) HIGH
Data setup to P0.1 (PROG) LOW
Data hold after P0.1 (PROG) HIGH
V_PP setup to P0.1 (PROG) LOW
V_PP hold after P0.1 (PROG) HIGH
P0.1 (PROG) width
V_PP (V_DD) LOW to data valid
P0.1 (PROG) HIGH to P0.1 (PROG) LOW
P0.0 (sync pulse) LOW
P0.0 (sync pulse) HIGH
ASEL HIGH time
Address hold time
Address setup to ASEL
Low address to address stable
MIN.
1.2
10 + 24t_CLCL
48t_CLCL
38t_CLCL
36t_CLCL
10
10
90
−
10
4t_CLCL
8t_CLCL
13t_CLCL
2t_CLCL
13t_CLCL
13t_CLCL
Note
1. Address should be valid at least 24t_CLCL before the rising edge of P0.0 (V_PP).
MAX.
6
−
−
−
−
−
−
110
48t_CLCL
−
−
−
−
−
−
−
UNIT
MHz
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
handbook, full pagewidth
P0.0 [V (p-p)] ^{5 V}
P0.1 (PROG)
P0.2 (ASEL)
PORT 2
PORT 3
12.75 V
tSHGL
25 PULSES
5V
tGHSL
tMASEL
tGLGH
tGHGL
98µs MIN 10µs MIN
tHASET
tHAHLD
HIGH ADDRESS
tADSTA
LOW ADDRESS
tDVGL
tGHDX
tAVQV
INVALID DATA
verify mode
VALID DATA
DATA TO BE
PROGRAMMED
program mode
Fig.11 Program/Verify cycle.
INVALID DATA VALID DATA
verify mode
MBE769
1996 Mar 22
29