83C145 Datasheet, PDF (6/40 Pages) NXP Semiconductors – Microcontrollers for TV and video MTV

Philips Semiconductors
Microcontrollers for TV and video (MTV)
Product specification
83C145; 83C845
83C055; 87C055
6.2 Pin description
Table 2 Pin description SDIP42 (SOT270-1)
SYMBOL
PIN
DESCRIPTION
Port 0 (notes 1, 2 and 4)
P0.0/TDAC/V_PP
1
P0.1/PWM1/PROG 2
P0.2/PWM2/ASEL
3
P0.3/PWM3
to
P0.7/PWM7
4 to 8
P0.0: open-drain bidirectional port line;
TDAC: output for the 14-bit high-precision PWM;
V_PP: 12 V programming supply voltage during EPROM programming.
P0.1: open-drain bidirectional port line;
PWM1: output for the 6-bit lower-precision PWM;
PROG: input for EPROM programming pulses.
P0.2: open-drain bidirectional port line;
PWM2: output for the 6-bit lower-precision PWM;
ASEL: input indicating the EPROM address bits that are applied to Port 2.
P0.3 to P0.7: 5 open-drain bidirectional port lines;
PWM3 to PWM7: 5 outputs for the 6-bit lower-precision PWM.
Port 1 (notes 1, 2 and 5)
P1.0/ADI0
to
P1.2/ADI2
P1.3/PWM0
9 to 11 P1.0 to P1.2: 3 open-drain bidirectional port lines;
ADI0 to ADI2: inputs for the software analog-to-digital facility.
12 P1.3: open-drain bidirectional port line; PWM0: output for the 6-bit lower-precision
PWM. PWM0 can be externally pulled up as high as +12 V ±5%
Port 2
P2.7 to P2.0
13 to 20 Port 2: 8-bit open-drain bidirectional port; P2.3 to P2.0 have high current capability
(10 mA at 0.5 V) for driving LEDs. Port 2 pins that have logic 1s written to them float,
and in that state can be used as high-impedance inputs. Any of the Port 2 pins are
driven LOW if the port register bit is written as a logic 0. The state of the pin can
always be read from the port register by the program.
Port 3 (note 1 and 3)
P3.0
34 P3.0: open-drain bidirectional port line.
P3.1/INT1
35 P3.1: open-drain bidirectional port line; INT1: External interrupt 1.
P3.2/T0
36 P3.2: open-drain bidirectional port line; T0: Timer 0 external input.
P3.3/INT0
37 P3.3: open-drain bidirectional port line; INT0: External interrupt 0.
P3.4 to P3.7
38 to 41 P3.4 to P3.7: 4 open-drain bidirectional port lines.
General
V_SS
VID2 to VID0
VCTRL
21 Ground: 0 V reference.
22 to 24 Digital Video bus: Three totem-pole outputs comprising digital RGB (or other colour
encoding) from the OSD facility. The polarity of these outputs is controlled by a
programmable register bit (register OSCON; bit Po).
25 Video Control: A totem-pole output indicating whether the OSD facility is currently
presenting active video on the VID2 to VID0 outputs. Signal is used to control an
external multiplexer (mixer) between normal video and the video derived from VID2 to
VID0. The polarity of this output is controlled by a programmable register bit (register
OSCON; bit Pc).
1996 Mar 22
6