83C145 Datasheet, PDF (26/40 Pages) NXP Semiconductors – Microcontrollers for TV and video MTV

Philips Semiconductors
Microcontrollers for TV and video (MTV)
Product specification
83C145; 83C845
83C055; 87C055
14 PROGRAMMING CONSIDERATIONS
14.1 EPROM Characteristics
The 87C055 is programmed by using a modified Quick-Pulse Programming algorithm similar to that used for devices
such as the 87C751. It differs from these devices in that a serial data stream is used to place the 87C055 in the
programming mode.
Figure 9 shows a block diagram of the programming configuration for the 87C055.
Table 31 Pin usage for Programming
PIN
USAGE
XTAL1
RESET
Oscillator input and receives the master system clock. This clock should be between
1.2 and 6 MHz.
Used to accept the serial data stream that places the 87C055 into various programming modes.
This pattern consists of a 10-bit code with the LSB sent first. Each bit is synchronized to the
clock input, XTAL1.
Port 0
V_PP/TDAC/P0.0 Used as the programming voltage supply input (V_PP signal).
PROG/PWM1/P0.1 Used as the program PROG signal. This pin is used for the 25 programming pulses.
Port 2
P2.7 to P2.0
Address input for the byte to be programmed and accepts both the high- and low-order
components of the 11-bit address; note 1.
Port 3
P3.7 to P3.0
Used as a bidirectional data bus during programming and verify operations. During programming
mode, it accepts the byte to be programmed. During verify mode, it provides the contents of the
EPROM location specified by the address which has been supplied to Port 2.
Note
1. Multiplexing of these address components is performed using the ASEL input:
a) ASEL input is driven HIGH and then drive Port 2 with the high-order bits of the address. ASEL should remain
HIGH for at least 13 clock cycles.
b) ASEL may then be driven LOW which latches the high-order bits of the address internally. The high-order address
should remain on Port 2 for at least 2 clock cycles after ASEL is driven LOW.
c) Port 2 may then be driven with the low byte of the address. The low-order address will be internally stable 13 clock
cycles later. The address will remain stable provided that the low byte placed on Port 2 is held stable and ASEL
is kept LOW.
d) ASEL needs to be pulsed HIGH only to change the high byte of the address.
1996 Mar 22
26