TDA8004T Datasheet, PDF (8/24 Pages) NXP Semiconductors – IC card interface

Philips Semiconductors
IC card interface
Product specification
TDA8004T
I/O circuitry
The three data lines I/O, AUX1 and AUX2 are identical.
The Idle state is realized by both lines (I/O and I/OUC)
being pulled HIGH via a 10 kΩ resistor (I/O to V_CC and
I/OUC to V_DD).
I/O is referenced to V_CC and I/OUC to V_DD, thus allowing
operation with V_CC ≠ V_DD.
The first side on which a falling edge occurs becomes the
master. An anti-latch circuit disables the detection of falling
edges on the other line, which becomes a slave.
After a time delay t_d(edge) (approximately 200 ns), the
N transistor on the slave side is turned on, thus
transmitting the logic 0 present on the master side.
When the master side returns to logic 1, the P transistor on
the slave side is turned on during the time delay t_d(edge) and
then both sides return to their Idle states.
This active pull-up feature ensures fast LOW-to-HIGH
transitions; it is able to deliver more than 1 mA up to an
output voltage of 0.9V_CC on a 80 pF load. At the end of the
active pull-up pulse, the output voltage only depends on
the internal pull-up resistor and on the load current (see
Fig.4).
The maximum frequency on these lines is 1 MHz.
6
handbook, halfpage
Vo
(V)
(1)
4
FCE270
12
Io
(mA)
(2)
8
2
4
0
0
20
(1) Current.
(2) Voltage.
0
40
60
t (ns)
Fig.4 I/O, AUX1, and AUX2 output voltage and
current as a function of time during a
LOW-to-HIGH transition.
Inactive state
After power-on reset, the circuit enters the inactive state. A
minimum number of circuits are active while waiting for the
microcontroller to start a session.
• All card contacts are inactive (approximately 200 Ω to
GND)
• I/OUC, AUX1UC and AUX2UC are high impedance
(10 kΩ pull-up resistor connected to V_DD)
• Voltage generators are stopped
• XTAL oscillator is running
• Voltage supervisor is active.
Activation sequence
After power-on and after the internal pulse width delay, the
system controller may check the presence of the card with
the signal OFF (OFF = HIGH while CMDVCC is HIGH
means that the card is present; OFF = LOW while
CMDVCC is HIGH means that no card is present).
If the card is in the reader (which is the case if PRES or
PRES is true), the system controller may start a card
session by pulling CMDVCC LOW.
The following sequence then occurs (see Fig.5):
• CMDVCC is pulled LOW (t₀)
• The voltage doubler is started (t₁ ~ t₀)
• V_CC rises from 0 to 5 V with a controlled slope
(t₂ = t₁ + ¹â„₂3T) (I/O, AUX1 and AUX2 follow V_CC with a
slight delay)
• I/O, AUX1 and AUX2 are enabled (t₃ = t₁ + 4T)
• CLK is applied to the C3 contact (t₄)
• RST is enabled (t₅ = t₁ + 7T).
In the timing informations above and below, T is 64 times
the period of the internal oscillator, about 25 µs.
The clock may be applied to the card in the following way:
• Set RSTIN HIGH before setting CMDVCC LOW and
reset it LOW between t₃ and t₅; CLK will start at this
moment. RST will remain LOW until t₅, where RST is
enabled to be the copy of RSTIN. After t₅, RSTIN has no
further action on CLK. This is to allow a precise count of
CLK pulses before toggling RST.
If this feature is not needed, then CMDVCC may be set
LOW with RSTIN LOW. In this case, CLK will start at t₃ and
after t₅, RSTIN may be set HIGH in order to get the Answer
To Request (ATR) from the card.
1999 Dec 30
8