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TDA8004T Datasheet, PDF (14/24 Pages) NXP Semiconductors – IC card interface
Philips Semiconductors
IC card interface
Product specification
TDA8004T
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Crystal connections (XTAL1 and XTAL2)
Cext
external capacitance on
XTAL1 and XTAL2
depending on specification −
−
of crystal or resonator used
fi(XTAL)
VIH(XTAL)
VIL(XTAL)
crystal input frequency
HIGH-level input voltage on XTAL1
LOW-level input voltage on XTAL1
2
−
0.8VDD −
−0.3
−
Data lines (I/O, I/OUC, AUX1, AUX2, AUXUC1 and AUXUC2)
15
pF
26
MHz
VDD + 0.2 V
0.2VDD V
GENERAL
td(edge)
delay between falling edge on pins
I/OUC and I/O (or I/O and I/OUC)
and width of active pull-up pulse
−
200 −
ns
fI/O(max)
Ci
maximum frequency on data lines
input capacitance on data lines
−
−
1
MHz
−
−
10
pF
DATA LINES; I/O, AUX1 AND AUX2 (WITH 10 KΩ PULL-UP RESISTOR CONNECTED TO VCC)
VOH
HIGH-level output voltage on data no DC load
lines
IOH = −40 µA
VOL
LOW-level output voltage on data I = 1 mA
lines
0.9VCC −
0.75VCC −
−
−
VCC + 0.1 V
VCC + 0.1 V
300
mV
VIH
HIGH-level input voltage on data
lines
1.8
−
VCC + 0.3 V
VIL
LOW-level input voltage on data
lines
−0.3
−
+0.8
V
Vinactive
Iedge
voltage on data lines outside a
no load
−
session
II/O = 1 mA
−
current from data lines when active VOH = 0.9VCC; Co = 80 pF −1
pull-up active
−
0.1
V
−
0.3
V
−
−
mA
ILIH
input leakage current HIGH on data VIH = VCC
lines
−
−
10
µA
IIL
LOW-level input current on data
VIL = 0 V
lines
−
−
600
µA
Rpu(int)
tr, tf
internal pull-up resistance between
9
data lines and VCC
input transition times on data lines from VIL(max) to VIH(min)
−
output transition times on data lines Co = 80 pF, no DC load;
−
10% to 90% of VCC (see
Fig.9)
11 13
kΩ
−
1
µs
−
0.1
µs
DATA LINES; I/OUC, AUX1UC AND AUX2UC (WITH 10 KΩ PULL-UP RESISTOR CONNECTED TO VDD)
VOH
HIGH-level output voltage on data no DC load
lines
IOH = −40 µA
VOL
LOW-level output voltage on data IOL = 1 mA
lines
0.9VDD −
0.75VDD −
−
−
VDD + 0.2 V
VDD + 0.2
300
mV
1999 Dec 30
14