TDA8004T Datasheet, PDF (7/24 Pages) NXP Semiconductors – IC card interface

Philips Semiconductors
IC card interface
Product specification
TDA8004T
handbook, full pagewidth
VDD
ALARM
(internal signal)
Vth2 + Vhys(th2)
Vth2
tW
tW
MGM176
Fig.3 ALARM as a function of V_DD (t_W = 10 ms).
Clock circuitry
The clock signal (CLK) to the card is either derived from a
clock signal input on pin XTAL1 or from a crystal up to
26 MHz connected between pins XTAL1 and XTAL2.
The frequency may be chosen at
f_XTAL, ¹â„₂f_XTAL, ¹â„₄f_XTAL or ¹â„₈f_XTAL via pins CLKDIV1 and
CLKDIV2.
The frequency change is synchronous, which means that
during transition, no pulse is shorter than 45% of the
smallest period and that the first and last clock pulse
around the change has the correct width.
In the case of f_XTAL, the duty factors are dependent on the
signal at XTAL1.
In order to reach a 45% to 55% duty factor on pin CLK the
input signal on XTAL1 should have a duty factor of
48% to 52% and transition times of less than 5% of the
input signal period.
If a crystal is used with f_XTAL, the duty factor on pin CLK
may be 45% to 55% depending on the layout and on the
crystal characteristics and frequency.
In the other cases, it is guaranteed between 45% and 55%
of the period.
The crystal oscillator runs as soon as the IC is powered up.
If the crystal oscillator is used, or if the clock pulse on
XTAL1 is permanent, then the clock pulse will be applied
to the card according to the timing diagram of the
activation sequence (see Fig.5).
If the signal applied to XTAL1 is controlled by the system
controller, then the clock pulse will be applied to the card
when the system controller will send it (after completion of
the activation sequence).
Table 1 Clock circuitry definition
CLKDIV1
0
0
1
1
CLKDIV2
0
1
1
0
CLK
1_⁄8fXTAL
1_⁄4fXTAL
1_⁄2fXTAL
f_XTAL
1999 Dec 30
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