SAA7372 Datasheet, PDF(8/60 Page) NXP Semiconductors – Digital servo processor and Compact Disc decoder CD7

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SAA7372 Datasheet, PDF (8/60 Pages) NXP Semiconductors – Digital servo processor and Compact Disc decoder CD7

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Philips Semiconductors

Digital servo processor and Compact Disc

decoder (CD7)

Product speciï¬cation

SAA7372

7 FUNCTIONAL DESCRIPTION

7.1 Decoder part

7.1.1 PRINCIPLE OPERATIONAL MODES OF THE DECODER

The decoding part can operate at different disc speeds,

single-speed (n = 1) and double-speed (n = 2). The factor

ânâ is called the overspeed factor.

A simplified data flow through the decoder part is

illustrated in Fig.6.

7.1.2 DECODING SPEED AND CRYSTAL FREQUENCY

The SAA7372 is a multi-speed decoding device, with an

internal phase-locked loop (PLL) clock multiplier.

Depending on the crystal frequency used and the internal

clock settings (selectable via register B), two playback

speeds shown in Table 1 are possible, where ânâ is the

overspeed factor.

An internal clock multiplier is present, controlled by

SELPLL, and should only be used if an 8.4672 MHz

crystal, ceramic resonator or external clock is present.

7.1.3 LOCK-TO-DISC MODE

For high speed CD-ROM applications, the SAA7372 has a

special mode, the lock-to-disc mode. This allows Constant

Angular Velocity (CAV) disc playback with varying input

data rates from the inside-to-outside of the disc. In the

lock-to-disc mode, the FIFO is blocked and the decoder

will adjust its output data rate to the disc speed. Hence, the

frequency of the I2S-bus clocks (WCLK and SCLK) are

dependent on the disc speed. In the lock-to-disc mode

there is a limit on the maximum variation in disc speed that

the SAA7372 will follow. Disc speeds must always be

within 25 to 100% range of their nominal value. The

lock-to-disc mode is enabled/disabled by register E.

7.1.4 STANDBY MODES

The SAA7372 may be placed in two standby modes

selected by register B (it should be noted that the device

core is still active)

Standby 1: âCD-STOPâ mode. Most I/O functions are

switched off.

Standby 2: âCD-PAUSEâ mode. Audio output features

are switched off, but the motor loop, the motor output

and the subcode interfaces remain active. This is also

called a âHot Pauseâ.

In the standby modes the various pins will have the

following values;

MOTO1 and MOTO2: put in high-impedance, PWM

mode (standby 1 and reset, operating in standby 2). Put

in high-impedance, PDM mode (standby 1 and reset,

operating in standby 2).

SCL, SDA, SILD and RAB: no interaction. Normal

operation continues.

SCLK, WCLK, DATA, EF, CL11 and DOBM: 3-state in

both standby modes. Normal operation continues after

reset.

CRIN, CROUT, CL16 and CL4: no interaction. Normal

operation continues.

V1, V2, V3, V4, V5, CFLG and C2FAIL: no interaction.

Normal operation continues.

Table 1 Playback speeds

00xx

01xx

10xx

11xx

SELPLL

CRYSTAL FREQUENCY (MHz)

33.8688

16.9344

8.4672

n=1

n=2

n=1

n = 2(2)

n=1

n=2

CL11 FREQUENCY

(MHz)(1)

11.2896

5.6448

11.2896

5.6448

Notes

1. The CL11 output is always a 5.6448 MHz clock if a 16.9344 MHz external clock is used and SELPLL = 0.

2. Data capture performance is not optimized for these options.

1998 Feb 26

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