SAA7372 Datasheet, PDF (12/60 Pages) NXP Semiconductors – Digital servo processor and Compact Disc decoder CD7

Philips Semiconductors
Digital servo processor and Compact Disc
decoder (CD7)
Product specification
SAA7372
7.5 Subcode data processing
7.5.1 Q-CHANNEL PROCESSING
The 96-bit Q-channel word is accumulated in an internal
buffer. The last 16 bits are used internally to perform a
Cyclic Redundancy Check (CRC). If the data is good, the
SUBQREADY-I signal will go LOW. SUBQREADY-I can
be read via the SDA or STATUS pins, selected via
register 2. Good Q-channel data may be read from SDA.
7.5.2
EIAJ 3 AND 4-WIRE SUBCODE (CD GRAPHICS)
INTERFACES
Data from all the subcode channels (P-to-W) may be read
via the subcode interface, which conforms to
EIAJ CP-2401. The interface is enabled and configured as
either a 3-wire or 4-wire interface via register F. The
subcode interface output formats are illustrated in Fig.7,
where the RCK signal is supplied by another device such
as a CD graphics decoder.
7.5.3 V4 SUBCODE INTERFACE
Data of subcode channels, Q-to-W, may be read via pin V4
if selected via register D. The format is similar to RS232
and is illustrated in Fig.8. The subcode sync word is
formed by a pause of (200/n) µs minimum. Each subcode
byte starts with a logic 1 followed by 7 bits (Q-to-W). The
gap between bytes is variable between (11.3/n) µs and
(90/n) µs.
The subcode data is also available in the EBU output
(DOBM) in a similar format.
handbook, full pagewidth
SBSY
SFSY
RCK
SUB
SFSY
RCK
SUB
SF0
SF1
SF2
SF3
SF97
SF0
P-W
P-W
P-W
EIAJ 4-wire subcode interface
SF0
SF1
SF2
SF3
SF97
SF0
SFSY
RCK
SUB
P-W
P-W
P-W
EIAJ 3-wire subcode interface
P QR S T U VW
SF1
SF1
MBG410
1998 Feb 26
Fig.7 EIAJ subcode (CD graphics) interface format.
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