SAA7372 Datasheet, PDF (16/60 Pages) NXP Semiconductors – Digital servo processor and Compact Disc decoder CD7

Philips Semiconductors
Digital servo processor and Compact Disc
decoder (CD7)
Product specification
SAA7372
7.8 DAC interface
The SAA7372 is compatible with a wide range of digital-to-analog converters (DACs). Eleven formats are supported and
are given in Table 4. Figures 11 and 12 show the Philips I²S-bus and the EIAJ data formats respectively. When the
decoder is operated in lock-to-disc mode, the SCLK frequency is dependent on the disc speed factor ‘d’. All formats are
MSB first and f_s is (44.1 × n) kHz. The polarity of the WCLK and the data can be inverted; selectable by register 7. It
should be noted that EF is only a defined output in CD ROM and 1f_s modes.
Table 4 DAC interface formats
REGISTER 3
1010
1011
1110
0010
0110
0000
0100
1100
0011
0111
1111
SAMPLE
FREQUENCY
f_s
f_s
f_s
f_s
f_s
4f_s
4f_s
4f_s
2f_s
2f_s
2f_s
NUMBER OF
BITS
16
16
16/18⁽¹⁾
16
18
16
18
18
16
18
18
SCLK (MHz)
FORMAT
2.1168 × n
2.1168 × n
2.1168 × n
2.1168 × n
2.1168 × n
8.4672 × n
8.4672 × n
8.4672 × n
4.2336 × n
4.2336 × n
4.2336 × n
CD ROM (I²S-bus)
CD ROM (EIAJ)
Philips I²S-bus; 16/18 bits⁽¹⁾
EIAJ 16 bits
EIAJ 18 bits
EIAJ 16 bits
EIAJ 18 bits
Philips I²S-bus; 18 bits
EIAJ 16 bits
EIAJ 18 bits
Philips I²S-bus; 18 bits
INTERPOLATION
no
no
yes
yes
yes
yes
yes
yes
yes
yes
yes
Note
1. In this mode the first 16 bits contain data, but if any of the fade, attenuate or de-emphasis filter functions are activated
then the first 18 bits contain data.
1998 Feb 26
16