SAA7372 Datasheet, PDF (10/60 Pages) NXP Semiconductors – Digital servo processor and Compact Disc decoder CD7

Philips Semiconductors
Digital servo processor and Compact Disc
decoder (CD7)
Product specification
SAA7372
crystal
clock
HF
2.2 kΩ
input
2.2 nF
47 pF
HFIN
DQ
22 kΩ
22 nF
HFREF
1/2VDD
Iref
100 µA
VSSA
VSS
100 nF
VSSA
ISLICE
100 µA
VDD
DPLL
MGA368 - 1
Fig.5 Data slicer showing typical application components (for n = 1).
7.4 Demodulator
7.4.1 FRAME SYNC PROTECTION
A double timing system is used to protect the demodulator
from erroneous sync patterns in the serial data. The
master counter is only reset if:
• A sync coincidence detected; sync pattern occurs
588 ±1 EFM clocks after the previous sync pattern
• A new sync pattern is detected within ±6 EFM clocks of
its expected position.
The sync coincidence signal is also used to generate the
PLL lock signal, which is active HIGH after 1 sync
coincidence found, and reset LOW if during 61
consecutive frames no sync coincidence is found.
The PLL lock signal can be accessed via the SDA or
STATUS pins selected by register 2 and 7.
Also incorporated in the demodulator is a Run Length 2
(RL2) correction circuit. Every symbol detected as RL2 will
be pushed back to RL3. To do this, the phase error of both
edges of the RL2 symbol are compared and the correction
is executed at the side with the highest error probability.
7.4.2 EFM DEMODULATION
The 14-bit EFM data and subcode words are decoded into
8-bit symbols.
1998 Feb 26
10