PDI1394L40 Datasheet, PDF (72/80 Pages) NXP Semiconductors – 1394 enhanced AV link layer controller

Philips Semiconductors
1394 enhanced AV link layer controller
Preliminary specification
PDI1394L40
15.0 AC CHARACTERISTICS
GND = 0 V, C_L = 50 pF
SYMBOL
PARAMETER
TEST CONDITIONS
t_PERIOD
(parallel
mode)
t_SU
t_IH
t_OD
t_WHIGH
t_WLOW
t_PWFS
t_SUP
t_HP
t_SCLKPER
t_DP
t_AS
t_AH
t_CL
t_CH
t_RP
t_ACC
t_DH
t_DS
t_DZ
t_WRP
t_WAIT
t_WWAIT
t_CWH
t_CWL
t_CP
t_CD
t_RESET
t_PWALE
t_ALES
t_ALEH
f_LPS
dc_LPS
AV clock period
AV clock setup time
AV clock input hold time
AV clock output delay time
AV clock pulse width HIGH
AV clock pulse width LOW
AVxFSYNC pulse width HIGH
PHY-link setup time
PHY-link hold time
SCLK period
PHY-link output delay
Host address setup time
Host address hold time
Host chip select pulse width LOW
Host chip select pulse width HIGH
Host read pulse width
Host access time
Host data hold time
Host data setup time
Host data bus release (Hi-Z)
Host write pulse width
WAIT output delay
WAIT pulse width
CYCLEIN HIGH pulse width
CYCLEIN LOW pulse width
CYCLEIN cycle period
CYCLEOUT cycle delay
RESET_N pulse width LOW
ALE pulse width
ALE setup time
ALE hold time
LPS signal frequency
LPS signal duty cycle
Note: C_L = 20 pF
WAVEFORMS
Figure 36
Figure 36
Figure 36
Figure 36
Figure 36
Figure 36
Figure 37
Figure 38
Figure 38
Figure 38
Figure 39
Figure 40
Figure 40
Figure 40
Figure 40
Figure 40
Figure 40
Figure 40
Figure 40
Figure 40
Figure 40
Figure 40
Figure 40
Figure 41
Figure 41
Figure 41
Figure 42
Figure 43
Figures 8, 9, 10
Figures 8, 9, 10
Figures 8, 9, 10
–
–
LIMITS
T_amb = 0 °C to +70 °C
MIN
TYP MAX
UNIT
41.67
ns
4
3
3
10
10
200
6.0
0
20.343
2.0
0
2
115
42
115
2
0
115
62
200
200
125
10
20
3
2
1.0
23
ns
ns
24
ns
300
20.345 20.347
10.0
115
15
12
20
2.75
28
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
µs
ns
ns
ns
MHz
%
2000 Dec 15
69