PDI1394L40 Datasheet, PDF (17/80 Pages) NXP Semiconductors – 1394 enhanced AV link layer controller

Philips Semiconductors
1394 enhanced AV link layer controller
Preliminary specification
PDI1394L40
12.5.2 Write accesses
To write to an internal register the host interface must collect the 4 byte values (8 bit mode) or 2 word values (16 bit mode) into a 32 bit value
and then write the result to the target register in a single clock tick. This requires a register to hold the 32 bit value being compiled until it is
ready to be written to the actual target register. This temporary register inside the host interface is called the shadow register. In 8 bit mode,
address lines HIF A0 and HIF A1 are used to select which of the 4 bytes of the shadow register is to be written with the value on the CPU data
bus. In 16 bit mode, HIF A1 is used to select which half of the shadow register is to be written with the value on the CPU data bus. Only one
byte (8 bit mode) or one word (16 bit mode) can be written in a single write access cycle.
Not all registers can be accessed in Direct Address Space. Some of the registers are in an indirect address space, these registers control the
FIFO size and content protection system. The correct internal register space has to be selected through the host interface, using directly
addressable registers INDADDR (0x0F8) and INDDATA (0x0FC).
MUX
TR
MUX
Q
8/16
32
CPU
Q
HIF A0..1 (8 BIT MODE)
HIF A1 (16 BIT MODE)
HIF A2..7
HIF A8
UPDATE/COPY CONTROL
REGISTERS
32
SV01035
NOTES:
1. It is not required to write all 4 bytes, or both words of a register: those bytes that are either reserved (undefined) or don’t care do not have
to be written in which case they will be assigned the value that was left in the corresponding byte of the shadow register from a previous
write access. For example, to acknowledge an interrupt for the isochronous receiver in 8 bit mode, a single byte write to location
0x100+(0x4C)+3 = 0x14F is sufficient. The value 256 represents setting HIF A8=1. The host interface cannot directly access the FIFOs, but
instead reads from/writes into a transfer register (shown as TR in the Figures above). Data is moved between FIFO and TR by internal logic
as soon as possible without CPU intervention.
2. The update control line does not necessarily have to be connected to the CPU address line HIF A8. This input could also be controlled by
other means, for example a combinatorial circuit that activates the update control line whenever a write access is done for byte 3 or the
upper 16 bits. This makes the internal updating automatic for quadlet writing.
3. Writing the bytes or words of the shadow register can be done in any order and as often as needed (new writes simply overwrite the old
value).
4. It is now possible to read/modify/write a register using the shadow register (0x0F4) without rewriting all 4 bytes. For example, to modify an
enable bit in the fourth byte of the Asynchronous Interrupt Enable (0x0A4), a read of location 0x100+0x0A0+3=0x1A3, followed by a write of
the modified byte to the same location 0x100+0x0A0+3=0x1A3 is sufficient. The other bytes remain unchanged.
12.5.3 Accessing the RDI register (Power–down, Power–up)
Accessing the RDI register is a special situation, but software written to access all other link base registers can still be used. This register can
be read and written with the link chip in power–down mode; this means that there is no system clock present within the link chip. The system
clock is required to access all other link registers due to the fact that multiple clock cycles are required to fetch data to the shadow register or
write data from the shadow register to the targeted internal register. Reading and writing to the RDI register is done through purely combinatoral
logic, there is no access through the shadow register. The RDI register is accessed directly through the host interface using the same method of
access required by other link base registers.
The RDI register contains control, status and interrupt bits. Operation of the status and interrupt bits in the RDI register differs slightly from these
types of bits in other registers. Operation falls into four categories: (1) pure status bit, (2) interrupt/status bit, (3) control bit, (4) interrupt control
bit.
LPSTAT is a pure status bit; this means that LPSTAT continually reflects the status of the LPS signal on the link–phy interface. If LPSTAT = 1,
the LPS signal is active. If LPSTAT = 0, the LPS signal to the phy chip is inactive. It should be noted here that the LPSTAT bit should NOT be
used as an indicator of link chip activity because the LPS signal may be inactive for short (25 uS) periods of time if the link chip is performing a
phy–link interface reset function. SCI is also a pure status bit when it is not enabled as an interrupt. SCI will reflect the INVERSE status of the
system clock at all times. When the system clock (SCLK) is active, SCI = 0. When the SCLK is inactive, SCI = 1. The SCI bit can also be used
as an interrupt bit by setting ESCI = 1. In this mode of operation when the SCI = 1, an interrupt will be generated to indicate that the SCLK has
become inactive. This interrupt is serviced in the same manner as all other link register interrupts... write a “1” back to the SCI bit position in
order to acknowledge the interrupt.
PLI, LOA and SCA are interrupt/status bits. These bits may be enabled as interrupts (by setting the corresponding interrupt control bit EPLI,
ELOA, or ESCA =1). These bits are ALSO status bits when the corresponding interrupt enabling bit is = 0. However, if any of these bits sets
(=1) while in the status bit mode, it must be written with a “1” to be reset... similar operation to interrupt bit operation elsewhere in the link
registers. Also, like other interrupt bits in the link registers, in order to acknowledge an interrupt of any of these bits, it is necessary to write a “1”
back to the bit position to acknowledge the interrupt; this resets the bit to “0”. [Please bear in mind that the functions represented by these bits
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