PDI1394L40 Datasheet, PDF (43/80 Pages) NXP Semiconductors – 1394 enhanced AV link layer controller

Philips Semiconductors
1394 enhanced AV link layer controller
Preliminary specification
PDI1394L40
12.7.1.1 Interrupt Hierarchy
HIF INT_N
3 21 0
GLOBCSR (0x018)
20 18 17 16 15 14 13 10 9 8 7 6 5 4 3 2 1 0
LNKPHYINTACK (0x008)
14 10 9 8 7 6 5 4 3 2 1 0
IRXINTACK (0x04C)
9876 543 21 0
ITXINTACK (0x02C)
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYINTACK (0x0A0)
NOTE:
1. A read of the RDI register (0xB0) should be done before looking for an interrupt in the GLOBCSR register.
Figure 33. Interrupt Hierarchy
SV01837
13.0 REGISTER MAP
Registers are 32 bits (quadlet) wide and all accesses are always done on a quadlet basis. This means that it is not possible to write just the
lower 8 bits, and leave the other bits unaffected (see Section 12.5.2 for more information). The values written to undefined fields/bits are ignored
and thus DON’T CARE.
A full bitmap of all registers is listed in Table 6. The meaning of shading and bit cell values is as follows:
A bit/field with no name written in it and dark shading is reserved and not used.
A bit/field with a name in it and light shading is a READ ONLY (status) bit/field.
A one bit value (0 or 1) written at the bottom of a writable (control) bit is the default value after power-on-reset.
Table 6. Full Bitmap of all Registers (consists of four tables shown on the following pages)
2000 Dec 15
40