PDI1394L40 Datasheet, PDF (6/80 Pages) NXP Semiconductors – 1394 enhanced AV link layer controller

Philips Semiconductors
1394 enhanced AV link layer controller
Preliminary specification
PDI1394L40
6.0 FUNCTIONAL DIAGRAM
HIF A[7:0]
HIF D[15:8]
HIF AD[7:0]
HIF A8
HIF WRN
HIF RDN
HIF CSN
HIF 16BIT
HIF MUX
RESETN
HIF ALE
HIF WAIT
HIF INTN
PD
CYCLEIN
CYCLEOUT
CLK50
AV1 D[7:0]
AV1CLK
AV1VALID
AV1SYNC
AV1FSYNC
AV1 SY
AV1READY
AV1ENDPCK
AV1ERR0
AV1ERR1
PDI1394L40
IEEE 1394
ENHANCED
AV LINK LAYER CONTROLLER
7.0 INTERNAL BLOCK DIAGRAM
AV1 D[7:0]
AV1READY
AV1CLK
AV1SYNC
AV1VALID
AV1FSYNC
AV1ENDPCK
AV1ERR0
AV1ERR1
AV1SY
AV1 LAYER
ISOCHRONOUS
TRANSMITTER/
RECEIVER
AV2 D[7:0]
AV2READY
AV2CLK
AV2SYNC
AV2VALID
AV2FSYNC
AV2ENDPCK
AV2ERR0/LTLEND
AV2ERR1/DATAINV
AV2SY
AV2 LAYER
ISOCHRONOUS
TRANSMITTER/
RECEIVER
HIF A[7:0]
HIF A8
HIF D[15:8]
HIF AD[7:0]
HIF 16BIT
HIF WRN
HIF ALE
HIF RDN
HIF MUX
HIF CSN
HIF WAIT
HIF INTN
8-BIT
INTERFACE
12KB BUFFER
MEMORY
(ISOCH & ASYNC
PACKETS)
ASYNC
TRANSMITTER
AND
RECEIVER
PHY D[0:7]
PHY CTL[0:1]
LPS
LREQ
ISON
LinkOn
SCLK
1394MODE
VDD
GND
AV2D[7:0]
AV2CLK
AV2VALID
AV2SYNC
AV2FSYNC
AV2 SY
AV2READY
AV2ENDPCK
AV2ERR0/LTLEND
AV2ERR1/DATAINV
SV01833
LINK CORE
CYCLEOUT
LPS
CYCLEIN
PHY D[0:7]
PHY CTL[0:1]
LREQ
LinkOn
ISON
PD
SCLK
1394MODE
NOTE: THERE IS ONE
ISOCHRONOUS RECEIVER
AND ONE ISOCHRONOUS
TRANSMITTER—THEREFORE,
WHEN EITHER AVPORT IS SET
TO TRANSMIT, THE OTHER
AVPORT IS AUTOMATICALLY
SET TO RECEIVE
CONTROL
AND
STATUS
REGISTERS
RESETN
SV01834
2000 Dec 15
3