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| PSMNR90-30BL_15 Datasheet, PDF (6/13 Pages) NXP Semiconductors – N-channel 30 V 1.0 mΩ logic level MOSFET in D2PAK | |||
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NXP Semiconductors
PSMNR90-30BL
N-channel 30 V 1.0 m⦠logic level MOSFET in D2PAK
Symbol
Parameter
Conditions
Ciss
input capacitance
VDS = 15 V; VGS = 0 V; f = 1 MHz;
Coss
output capacitance
Tj = 25 °C; Fig. 16
Crss
reverse transfer
capacitance
td(on)
turn-on delay time
VDS = 15 V; RL = 0.2 Ω; VGS = 5 V;
RG(ext) = 5 Ω; ID = 75 A; Tj = 25 °C
tr
rise time
VDS = 15 V; RL = 0.2 Ω; VGS = 5 V;
RG(ext) = 5 Ω; Tj = 25 °C; ID = 75 A
td(off)
tf
turn-off delay time
fall time
VDS = 15 V; RL = 0.2 Ω; VGS = 5 V;
RG(ext) = 5 Ω; ID = 75 A; Tj = 25 °C
Source-drain diode
VSD
source-drain voltage IS = 25 A; VGS = 0 V; Tj = 25 °C; Fig. 17
trr
reverse recovery time IS = 25 A; dIS/dt = -100 A/µs; VGS = 0 V;
Qr
recovered charge
VDS = 15 V
300
gfs
(S)
240
003aaf762
105
C
(pF)
180
104
120
Min Typ Max Unit
-
14850 -
pF
-
2799 -
pF
-
1215 -
pF
-
95
-
ns
-
213 -
ns
-
199 -
ns
-
115 -
ns
-
0.8 1.2 V
-
67
-
ns
-
123 -
nC
003aaf766
Ciss
Crss
60
0
0
20
40
60
80
ID (A)
Fig. 5. Forward transconductance as a function of
drain current; typical values
103
10-1
1
10 VGS(V) 102
Fig. 6. Input and reverse transfer capacitances as a
function of gate-source voltage; typical values
PSMNR90-30BL
Product data sheet
All information provided in this document is subject to legal disclaimers.
2 April 2014
© NXP Semiconductors N.V. 2014. All rights reserved
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