SAA2520 Datasheet, PDF (4/36 Pages) NXP Semiconductors – Stereo filter and codec for MPEG layer 1 audio applications

Philips Semiconductors
Stereo filter and codec for MPEG layer 1
audio applications
Preliminary specification
SAA2520
PINNING
SYMBOL
FS256
MUTEDAC
DEEMDAC
ATTDAC
V_SS
URDA
SBDIR
SBDA
SBCL
SBWS
SBEF
SBMCLK
SYNCDAI
FDIR
FRESET
FSYNC
FDAF
FDAC
SCL
SWS
SDA
PWRDWN
DSC4
DSC3
DSC2
DSC1
DSC0
V_DD
RESET
T1
T0
LTDATA
LTCLK
PIN
DESCRIPTION
TYPE
1 (Filtered)-I²S clock; 256 × sample frequency. 12 mA 3-state output + CMOS
I/O
input with pull-down
2 DAC control/output expander
O
3 DAC control/output expander
O
4 DAC control/output expander
O
5 supply ground (0 V)
6 unreliable drive processing data; CMOS level
I
7 sub-band I²S direction: (SWBS, SBCL, SBDA); CMOS level
I
8 sub-band I²S data; 4 mA, 3-state output + CMOS input with pull-down
I/O
9 sub-band I²S bit clock; 4 mA, 3-state output + CMOS input with pull-down
I/O
10 sub-band I²S word select; 4 mA, 3-state output + CMOS input with pull-down
I/O
11 sub-band I²S byte error flag; CMOS level
I
12 sub-band I²S clock, 6.144 MHz locked to FS256; 8 mA, 3-state output + CMOS O
input with pull-down
13 DAI synchronization pulse
O
14 (Filtered)-I²S direction: (FDAC, FDAF, SDA);
O
15 reset signal for SAA2521
O
16 Filtered-I²S sync signal for SAA2521
O
17 Filtered-I²S sub-band filter data; 4 mA, 3-state output + CMOS input with
I/O
pull-down
18 Filtered-I²S sub-band codec data; 4 mA, 3-state output + CMOS input with
I/O
pull-down
19 I²S bit clock; 4 mA, 3-state output + CMOS input with pull-down
I/O
20 I²S-word select; 4 mA, 3-state output + CMOS input with pull-down
I/O
21 I²S baseband data filter; 4 mA, 3-state output + CMOS input with pull-down
I/O
22 power-down mode; CMOS level
I
23 test pin
24 test pin
25 test pin
26 test pin
27 test pin
28 positive supply voltage (+5 V)
29 system reset; CMOS level with pull-down and hysteresis
I
30 test pin; do not connect
31 test pin; do not connect
32 LT interface data; 4 mA, 3-state output + CMOS input with pull-down
I/O
33 LT interface bit clock; CMOS level
I
August 1993
4