SAA2520 Datasheet, PDF (13/36 Pages) NXP Semiconductors – Stereo filter and codec for MPEG layer 1 audio applications

Philips Semiconductors
Stereo filter and codec for MPEG layer 1
audio applications
Preliminary specification
SAA2520
FS256
SCL
T
t _fH
t _fL
t _d1
SWS, SDA, FDAF, FDAC, FSYNC
output
SDA, FDAF, FDAC
input
t _sL
t _h2
t _d2
t _d1
Tc
t _su t _h1
t _sH
MEA642 - 3
Fig.11 Filtered I²S interface timing (master mode - FS256, SCL and SWS are input).
Notes to Fig.11
T
T_c
t_fH
t_fL
t_SH
t_SL
t_S
t_H1
t_H2
t_{D1, 2}
FS256 cycle time (f_s = 48 kHz)
FS256 cycle time (f_s = 44.1 kHz)
FS256 cycle time (f_s = 32 kHz)
SCL cycle time
FS256 HIGH time (f_s = 48 kHz)
FS256 HIGH time (f_s = 44.1 kHz)
FS256 HIGH time (f_s = 32 kHz)
FS256 LOW time (f_s = 48 kHz)
FS256 LOW time (f_s = 44.1 kHz)
FS256 LOW time (f_s = 32 kHz)
SCL HIGH time
SCL LOW time
SDA, FDAF, FDAC input set-up
before FS256 HIGH
SDA, FDAF, FDAC input hold
after FS256 HIGH
SDA, FDAF, FDAC output hold
after FS256 HIGH
FS256 HIGH to SCL, SWS,
SDA, FDAF, FDAC output valid
81.4 ns nominal
88.6 ns nominal
122.1 ns nominal
4T ns nominal
≥ 35 ns
≥ 38 ns
≥ 35 ns
≥ 35 ns
≥ 38 ns
≥ 75 ns
≥ 2T - 20 ns
≥ 2T - 20 ns
≥ 20 ns
≥ 30 ns
≤ 0 ns
≤ 50 ns
August 1993
13