SAA2520 Datasheet, PDF (11/36 Pages) NXP Semiconductors – Stereo filter and codec for MPEG layer 1 audio applications

Philips Semiconductors
Stereo filter and codec for MPEG layer 1
audio applications
Preliminary specification
SAA2520
Interface between SAA2520 and SAA2521 consists of the following signals:
FILTERED-I²S INTERFACE
SWS
SCL
FDAC
FDAF
FSYNC
bi-directional
bi-directional
bi-directional
bi-directional
output
word select (common to I²S)
bit clock (common to I²S)
codec data
filter data
synchronization
FS
64FS
FS/32
Filtered data is transferred between SAA2520 filter/codec
functions and the SAA2521 using the format shown in
Fig.9.
The frequency of the SWS signal is equal to the sample
frequency FS and the bit clock SCL is 64 times the sample
frequency. Each period of SWS contains 64 data-bits, 48
of which are used to transfer data. The half period in which
SWS is LOW is used to transfer the information of the
LEFT channel while the following half period during which
SWS is HIGH carries the data of the RIGHT channel.
The 24-bit samples are transferred most significant bit first.
This bit is transferred in the bit clock period with a 1-bit
delay following the change in SWS. Both SWS and
FDAF/FDAC change state at the negative edge of SCL.
The SAA2521 may be synchronized to the sub-band
codec using the FSYNC signal, which defines the SWS
period in which the samples of sub-band 0 (containing the
lowest frequency components) are transferred
(see Fig.10).
SAA2521 AND INPUT/OUTPUT MODE CONTROL
The operation of SAA2521 and the input/output circuitry is
controlled by three signals shown in Table 1.
MPEG CODED INTERFACE
The interface that carries the MPEG coded signal uses
the following signals:
The MPEG I²S interface
SBWS bi-directional word selection
SBCL bi-directional bit clock
SBDA bi-directional sub-band coded data
SBEF input
error signal
Operation is further controlled by:
SBDIR input
direction of data flow
URDA input
unreliable encoded data signal
The SBMCLK signal is the main frequency from which
other clock signals are derived. In encode mode this
division is performed internally. In decode mode the
external source should provide SBWS and SBCL.
The frequency of the signal is equal to 1/32nd of the bit
rate. The frequency of the bit clock SBCL is twice that of
the bit rate. Some examples of the frequencies are given
in Table 2.
FRESET and SYNCDAI are given whenever:
− FS256, SCL and SWS outputs switch between
high and low impedance
− FS256 frequency is changed
(12.288/11.2896/8.192 MHz)
− FDIR is switching
− bit rate is changing
− system reset is active
August 1993
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