SAA2520 Datasheet, PDF (18/36 Pages) NXP Semiconductors – Stereo filter and codec for MPEG layer 1 audio applications

Philips Semiconductors
Stereo filter and codec for MPEG layer 1
audio applications
Preliminary specification
SAA2520
SBMCLK
t _cL
 ^SBCL
SBWS
SBDA
t _d1 t _d2
tmL ^Ts t _mH
Tsc
t _cH
^{MEA645 - 2}
Fig.15 Sub-band I²S interface timing (master mode - SBCL, SBWS and SBDA are output).
Notes to Fig.15
T
SBMCLK cycle time
t_mH
SBMCLK HIGH time
t_mL
SBMCLK LOW time
T_c
SBCL cycle time (384 kB/s)
SBCL cycle time (256 kB/s)
SBCL cycle time (192 kB/s)
SBCL cycle time (128 kB/s)
t_CH
SBCL HIGH time (384 kB/s)
SBCL HIGH time (256 kB/s)
SBCL HIGH time (192 kB/s)
SBCL HIGH time (128 kB/s)
t_CL
SBCL LOW time (384 kB/s)
SBCL LOW time (256 k/Bs)
SBCL LOW time (192 kB/s)
SBCL LOW time (128 kB/s)
t_D1
SBWS, SBDA hold to SBCL LOW
t_D2
SBCL LOW to SBWS, SBDA valid
120 to 205 ns (163 ns nominal)
≥ 35 ns
≥ 75 ns
8T ns nominal
12T ns nominal
16T ns nominal
24T ns nominal
≥ 4T - 20 ns
≥ 6T - 20 ns
≥ 8T - 20 ns
≥ 12T - 20 ns
≥ 4T - 20 ns
≥ 6T - 20 ns
≥ 8T - 20 ns
≥ 12T - 20 ns
≤ 20 ns
≤ 20 ns
August 1993
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