SAA2520 Datasheet, PDF (28/36 Pages) NXP Semiconductors – Stereo filter and codec for MPEG layer 1 audio applications

Philips Semiconductors
Stereo filter and codec for MPEG layer 1
audio applications
Preliminary specification
SAA2520
handbook, full pagewidth
LTENA
LTCLK
LTCDATA
input
LTCDATA
output
t _el
t _D1
t _S1
t _H1
LTCNT0
LTCNT1
t _D5
t _CL
t _CH
t _S2
t _H2
t _D3
t _D2
hiZ
t _D6
t _H3
Fig.22 Microcontroller interface timing.
Notes to Fig.22
t_eL
t_CH
t_CL
t_D1
t_D2
t_D3
t_D4
t_H4
t_D5
t_D6
t_S1
t_H1
t_S2
t_H2
t_H3
t_H4
LTENA LOW time
LTCLK HIGH time
LTCLK LOW time
LTENA HIGH to LTCLK HIGH
LTENA HIGH to LTDATA
output low impedance
LTENA HIGH to LTDATA output valid
LTENA LOW to LTDATA high impedance
LTENA hold after LTCLK HIGH
LTCLK HIGH to LTENA HIGH
LTCLK HIGH to LTDATA output valid
for bit 0 (see Fig.21)
for first bit in the second 8-bit unit
LTCNT0/1 set-up before LTENA HIGH
LTCNT0/1 hold after LTENA HIGH
LTDATA set-up before LTCLK HIGH
LTDATA input hold after LTCLK HIGH
LTDATA output hold after LTCLK HIGH
LTENA hold after LTCLK HIGH
August 1993
28
t _H4
t _D4
hiZ
MLB135
≥ 190 ns
≥ 190 ns
≥ 190 ns
≥ 190 ns
≥ 0 ns
≤ 380 ns
≤ 50 ns
≥ 355 ns
≥ 190 ns
≤ 355 ns
≤ 520 ns
≥ 190 ns
≥ 190 ns
≥ 190 ns
≥ 30 ns
≥ 145 ns
≥ 355 ns