SAA2520 Datasheet, PDF (15/36 Pages) NXP Semiconductors – Stereo filter and codec for MPEG layer 1 audio applications

Philips Semiconductors
Stereo filter and codec for MPEG layer 1
audio applications
Preliminary specification
SAA2520

, ^FRESET
SYNCDAI
FDIR
t _d0
td2 t _d3
t _d4
HIGH Z
t _sH
SDA
t _d1
t _d5
HIGH Z
SDA
FDAF
FDAC
t _d6
HIGH Z ^SWS
FS256
SCL
HIGH Z
t _d7
t _d8
t _d9
HIGH Z
FDAF ^{HIGH Z}
FDAC
SWS
FS256
SCL
MEA646 - 1
Fig.13 Mode switch timing.
Notes to Fig.13
t_DO
FRESET HIGH to SYNCDAI HIGH
t_SH
SYNCDAI HIGH time
t_D1
SYNCDAI LOW to FRESET LOW
t_D2
FDIR hold to FRESET HIGH
t_D3
FRESET HIGH to FDIR valid
t_D4
SDA change to high impedance
after FRESET HIGH
t_D5
SDA remains high impedance
after FRESET LOW
t_D6
FDAF, FDAC change to high impedance
after FRESET HIGH
t_D7
FDAF, FDAC remain high impedance
≥ 300 ns
≥ 1280 ns
≥ 790 ns
≤ 20 ns
≤ 20 ns
≥ 0 ns
≤ 170 ns
≥ 0 ns
≤ 170 ns
≤ 20 ns
August 1993
15