SAA5281 Datasheet, PDF (3/48 Pages) NXP Semiconductors – Integrated Video input processor and Teletext decoder IVT1.8

Philips Semiconductors
Integrated Video input processor and
Teletext decoder (IVT1.8*)
BLOCK DIAGRAM
Preliminary specification
SAA5281
handbook, full pagewidth _{VDD1 VDD2}
1
10
POWER-ON
RESET
BLAN RGBREF
Y
COR
RGB
22 19 20 18 15 16 17
DISPLAY
DRAM
REFRESH
AND
TIMING
ODD/EVEN 21
(or DV)
8K x 8
DRAM
24 TO 18
HAMMING
DECODER
TELETEXT
AQUISITION
AND DECODING
SERIAL-TO
-PARALLEL
CONVERTER
PACKET 26
PROCESSING
ENGINE
VPS
ACQUISITION
AND
DECODING
SAA5281
MEMORY
INTERFACE
I ² C-BUS
INTERFACE
24
SDA
23
SCL
TIMING
CHAIN
44
LINE 23
DATA SLICER
AND CLOCK
REGENERATOR
TELETEXT
OR
VPS CONTROL
REF
IREF
6
9
ANALOG
REFERENCE
GENERATOR
ANALOG
TO
DIGITAL
CONVERTER
INPUT
CLAMP
AND SYNC
SEPARATOR
5
14
25
VSS1 VSS2
VSS3
8
CVBS
7
BLACK
ANALOG
OUTPUT
BUFFER
DISPLAY CLOCK
PHASE-LOCKED
LOOP
13
11
37
27 MHz
4
CLOCK
GENERATOR
VCR/FFB
POL
CLK O/P
OSCGND
12
36 2
3
STTV/LFB CLK EN
OSCIN
OSCOUT
MBD783
1996 Nov 04
Fig.1 Block diagram; pin numbers for DIP48 (SOT240-1).
3