SAA5281 Datasheet, PDF (25/48 Pages) NXP Semiconductors – Integrated Video input processor and Teletext decoder IVT1.8

Philips Semiconductors
Integrated Video input processor and
Teletext decoder (IVT1.8*)
Preliminary specification
SAA5281
Table 11 Register map for page requests (R3); notes 1 to 6
START
COLUMN
0
1
2
3
4
5
6
7
PRD4
DO CARE
Magazine
DO CARE
Page tens
DO CARE
Page units
DO CARE
Hours tens
DO CARE
Hours units
DO CARE
Minutes tens
DO CARE
Minutes units
X
PRD3
HOLD
PT3
PU3
SUBTITLE
HU3
X
MU3
X
PRD2
MAG2
PT2
PU2
X
HU2
MT2
MU2
CH2
PRD1
MAG1
PT1
PU1
HT1
HU1
MT1
MU1
CH1
PRD0
MAG0
PT0
PU0
HT0
HU0
MT0
MU0
CH0
Notes
1. Abbreviations are as given in Table 6 except for DO CARE bits and CH = chapter address for acquisition chapter.
2. When the DO CARE bit is set to logic 1 this means the corresponding digit is to be taken into account for page
requests. If the DO CARE bit is set to logic 0 the digit is ignored. This allows, for example, normal or timed page
selection.
3. If HOLD is set LOW, the page is held and not updated.
4. Columns auto-increment on successive I²C-bus transmission bytes.
5. The SUBTITLE bit is only present when the device is in ‘1.8 mode’ (i.e. R13D6 has been set HIGH).
6. X = don’t care.
Table 12 Acquisition channel programming
H0 to H3⁽¹⁾
S0 to S3⁽¹⁾
CHECKING ALGORITHM FOR ACQUISITION CHANNEL X
0
0
7-bit + parity for whole page
0
1
8-bit for whole page
1
0
8/4 Hamming check for whole page
1
1
mixed 8/4 Hamming (columns 0 to 7, 20 to 27) and 7-bit + parity
(columns 8 to 19, 28 to 39)
Note
1. These register bits operate in conjunction with 7 + P/ 8-BIT (Register 1, Bit D6) which will over-ride the choice of data
checker if set, setting all channels to 8-bit only. If this bit is not set H0 to H3 and S0 to S3 will determine the data
checking (default to 7-bit + parity).
1996 Nov 04
25