SAA5281 Datasheet, PDF (20/48 Pages) NXP Semiconductors – Integrated Video input processor and Teletext decoder IVT1.8

Philips Semiconductors
Integrated Video input processor and
Teletext decoder (IVT1.8*)
Preliminary specification
SAA5281
VPT data memory organization
To simplify the software for dual-standard VPT decoders,
the VPS data from line 16 is stored in row 25 of Chapter 5
of the page memory, and is aligned to match the
packet 8/30 format 2 data as far as possible. The 8/30
format 2 packet is Hamming coded and by setting the
appropriate register control bit the data is stored after
hardware Hamming correction. There are 4 data bits
stored in each column address of memory with an
additional Hamming error bit. The data equivalent to the
VPS signal is found in columns 12 to 19.
Although the VPS data is not Hamming protected, it is
stored with 4 data bits per column address in the same
way with an additional biphase error bit. The extra space
in Row 25 is allocated to two more Line 16 words.
They are Word 15 (reserved) and Word 4 (Program
Source Identification, ASCII sequential) which may be
useful for future applications. Details of the memory
organization are shown in Fig.12.
The stored data can be read from memory via the I²C-bus
in the normal way. Multiple reception/majority error
correction of the VPS data is the responsibility of the
control software, the device simply stores the data as
transmitted after biphase decoding.
As both VPS and 8/30/2 signals are stored in separate
memory locations, it is possible to deal with future
situations where both System A and System B
transmissions may be present on the same TV channel,
the defaults and level of service chosen by the control
software.
handbook, full pagewidth _column
8/30/2
VPS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
D
initial page
b13 b14 b15 b16 b17 b18 b19 b20 b21 b22 b23 b24 b25
received page information
B11 B12 B13 B14 B15
column
8/30/2
VPS
20 21 22 23 24 25 26 27 28 29 30 11 12 13 14 15 16 17 18 19
status display
B4
B5
MBD787
Fig.12 Detailed memory organization.
1996 Nov 04
20