SAA5281 Datasheet, PDF (18/48 Pages) NXP Semiconductors – Integrated Video input processor and Teletext decoder IVT1.8

Philips Semiconductors
Integrated Video input processor and
Teletext decoder (IVT1.8*)
Preliminary specification
SAA5281
Extension packet memory organization
When in normal extension packet enabled mode the rows of information are organized as illustrated in Fig.10.
Row 23 of the extension page, as shown in Fig.10, contains packet 8/30. Packet 8/30 is mapped into the IVT1.8* memory
as follows:
8 / 30 / 0 and 8 / 30 / 1 to Chapter 4 Row 23
8 / 30 / 2 and 8 / 30 / 3 to Chapter 5 Row 23
8 / 30 / 4 to 8 / 30 / 15 to Chapter 6 Row 23.
handbook, full pagewidth
PACKETS X/26/0 to X/26/14
PACKET X/28/2
PACKETS X/27/0 to X/27/1
PACKETS X/27/4 to X/27/5
PACKET X/24 IF R0D7 = 0
PACKET X/25
PACKET X/28/0
PACKET 8/30
PACKET X/28/1
RESERVED ⁽¹⁾
ROW
0
to
14
15
16
17
18
19
20
21
22
23
24
25
MBD791
(1) Row 25 reserved for VPS data in Chapter 5.
Fig.10 Organization of the extension memory.
1996 Nov 04
18