SAA5281 Datasheet, PDF (22/48 Pages) NXP Semiconductors – Integrated Video input processor and Teletext decoder IVT1.8

Philips Semiconductors
Integrated Video input processor and
Teletext decoder (IVT1.8*)
Preliminary specification
SAA5281
Notes to Table 7
1. The dash (−) indicates these bits are inactive and must be written to logic 0 for future compatibility.
2. Certain registers are auto-incremented following an I²C-bus transmission byte. These are Register R0 to R3,
R4 to R7 and R8 to R12 or R13.
3. All bits in Registers R0 to R13 are cleared to logic 0 on power-up except bits D0 and D1 of Registers R1, R5 and R6
which are set to logic 1.
4. All memory is cleared to space (00100000) on power-up, except Row 0 Column 7 Chapter 0, which is alpha white
(00000111) as the acquisition circuit is enabled but all pages are on hold.
Table 8 Register description
REGISTER BIT D0 TO D7
FUNCTION
R0 AVANCED CONTROL - auto-increments to Register 1
R11/R11B SELECT
Selects reading of R11 if LOW or R11B if HIGH.
VCR MODE
If logic 1 selects short time constant mode of PLL.
DISABLE ODD/EVEN
Forces ODD/EVEN output LOW when logic 1 (see Table 9).
CBB SLAVE SYNC
When set will modify internal slave sync timing to allow connection to sandcastle of
Philips one-chip TV IC (TDA8362).
DISABLE HDR ROLL
Stops the display update of rolling time and green rolling header during page
requests when logic 1. Time updates on page reception only.
AUTO ODD/EVEN
If logic 1 then ODD/EVEN output only active when no TV picture displayed
(see Table 9).
FREE RUN PLL
Will force the display PLL to free run at 6 MHz when logic 1.
X/24 POS
Automatic display of FASTEXT prompt row when logic 1. Will also cause Row 24
data transmitted by packet 26 to be written to display, rather than extension
memory.
R1 MODE - auto-increments to Register 2
T0, T1
TCS ON
DEW/FULL FIELD
EXT PKT ENABLE
Interlace/non-interlace 312/313 line control (see Table 10).
Text composite sync or direct sync select (see Table 10 for FFB mode selection).
Field-flyback or full-channel mode.
Enables reception and storage of extension packets when logic 1.
ACQ ON/OFF
7 + P/8-BIT
VCS TO SCS
Acquisition circuits turned off when logic 1.
7 bits with parity checking or 8-bit mode.
Connects VCS from video sync separator to display field sync detector to enable
stable display of 60 Hz status messages when logic 1.
R2 PAGE REQUEST ADDRESS - auto-increments to Register 3
SC0 to SC2
Start column for page request data (see Table 11).
0
Must be logic 0 for normal operation.
ACQ CCT A0, A1
Selects one of four acquisition circuits.
BANK SELECT A2
Selects bank of four pages being addressed for acquisition.
HAM CHECK 27, 8/30
8/4 Hamming check packet 27 and 8/30 data.
R3 PAGE REQUEST DATA - does not auto-increment
PRD0 to PRD4
See Table 11.
1996 Nov 04
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