PSMN006-20K Datasheet, PDF (3/12 Pages) NXP Semiconductors – TrenchMOS ultra low level FET

Philips Semiconductors
PSMN006-20K
TrenchMOS™ ultra low level FET
120
Pder
(%)
80
03aa17
120
Ider
(%)
80
03aa25
40
40
0
0
50
100
150
200
Tsp (°C)
P_der = _P-------^P----^t--^o---^t------- × 100%
t o t ( 25 ^°C )
Fig 1. Normalized total power dissipation as a
function of solder point temperature.
102
Limit RDSon = VDS / ID
ID
(A)
10
DC
1
0
0
50
100
150
200
Tsp (°C)
I_der = -_I-------^I--^D--------- × 100%
D ( 25 ^°C )
Fig 2. Normalized continuous drain current as a
function of solder point temperature.
tp = 10 µs
1 ms
10 ms
03ai63
100 ms
10-1
10-1
1
10
102
VDS (V)
T_sp = 25 °C; I_DM is single pulse.
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 09631
Product data
Rev. 01 — 30 May 2002
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
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