SAA7120H Datasheet, PDF (27/36 Pages) NXP Semiconductors – Digital video encoder

Philips Semiconductors
Digital video encoder
Product specification
SAA7120H; SAA7121H
8.1 Explanation of RTCI data bits
1. The HPLL increment is not evaluated by the
SAA7120H; SAA7121H.
2. The SAA7120H; SAA7121H generates the subcarrier
frequency from the FSCPLL increment if enabled
(see item 7.).
3. The PAL bit indicates the line with inverted (R − Y)
component of colour difference signal.
4. If the reset bit is enabled (RTCE = 1; DECPH = 1;
PHRES = 00), the phase of the subcarrier is reset in
each line whenever the reset bit of RTCI input is set to
logic 1.
5. If the FISE bit is enabled (RTCE = 1; DECFIS = 1), the
SAA7120H; SAA7121H takes this bit instead of the
FISE bit in subaddress 61H.
6. If the odd/even bit is enabled (RTCE = 1; DECOE = 1),
the SAA7120H; SAA7121H ignores its internally
generated odd/even flag and takes the odd/even bit
from RTCI input.
7. If the colour detection bit is enabled (RTCE = 1;
DECCOL = 1) and no colour was detected (colour
detection bit = 0), the subcarrier frequency is
generated by the SAA7120H; SAA7121H. In the other
case (colour detection bit = 1) the subcarrier
frequency is evaluated out of FSCPLL increment.
If the colour detection bit is disabled (RTCE = 1;
DECCOL = 0), the subcarrier frequency is evaluated
out of FSCPLL increment, independent of the colour
detection bit of RTCI input.
handbook, full pagewid^Hth^{IGH-to-LOW transition}
count start
RTCI
LOW HPLL
128
increment ⁽¹⁾
13
4 bits
reserved
0
22
time slot: 0 1
14
19
not used in SAA7120H/21H
FSCPLL increment ⁽²⁾
3 bits
reserved
0
(5)
(4)
(7)
(3)
(6)
valid
sample
invalid
sample
64 67 69 72 74
68
8/ LLC
MBH789 ⁽⁸⁾
(1) SAA7111/12 provides 14 to 0 bits, resulting in 2 reserved bits before FSCPLL increment.
(2) SAA7151 provides 21 to 0 bits only, resulting in 5 reserved bits before sequence bit.
(3) Sequence bit: PAL: 0 = (R − Y) line normal, 1 = (R − Y) line inverted; NTSC: 0 = no change.
(4) Reset bit: only from SAA7111 and SAA7112 decoder.
(5) FISE bit: 0 = 50 Hz, 1 = 60 Hz.
(6) Odd/even bit: odd_even from external.
(7) Colour detection: 0 = no colour detected, 1 = colour detected.
(8) Reserved bits: 229 with 50 Hz systems, 226 with 60 Hz systems.
Fig.9 RTCI timing.
2002 Oct 11
27