SAA7120H Datasheet, PDF (26/36 Pages) NXP Semiconductors – Digital video encoder

Philips Semiconductors
Digital video encoder
Product specification
SAA7120H; SAA7121H
handbook, full pagewidth
LLC clock output
LLC clock input
tHIGH
tHD; _DAT
tHIGH
input data
tHD; _DAT
tSU; _DAT
valid
output data
tHD; _DAT
valid
TLLC
tf
TLLC
tf
not valid
td
not valid
Fig.7 Clock data timing.
tr
tr
valid
2.6 V
1.5 V
0.6 V
2.4 V
1.5 V
0.8 V
2.0 V
0.8 V
valid
2.4 V
0.6 V
MBE742
handbook, full pagewidth
LLC
MP(n)
RCV2
CB(0)
Y(0)
CR(0)
Y(1)
CB(2)
MGB699
The data demultiplexing phase is coupled to the internal horizontal phase.
The phase of the RCV2 signal is programmed to 262 for 50 Hz and to 234 for 60 Hz in this example in output mode (RCV2S).
Fig.8 Functional timing.
2002 Oct 11
26