SAA7120H Datasheet, PDF (11/36 Pages) NXP Semiconductors – Digital video encoder

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DATA BYTE⁽¹⁾
REGISTER FUNCTION
SUBADDR
D7
D6
D5
D4
D3
D2
D1
D0
Line 21 even 0
Line 21 even 1
RCV port control
Trigger control
Trigger control
Multi control
Closed caption, teletext enable
RCV2 output start
RCV2 output end
MSBs RCV2 output
TTX request H start
TTX request H delay
Vsync shift
TTX odd request vertical start
TTX odd request vertical end
TTX even request vertical start
TTX even request vertical end
First active line
Last active line
MSB vertical
Null
Disable TTX line
Disable TTX line
69H
6AH
6BH
6CH
6DH
6EH
6FH
70H
71H
72H
73H
74H
75H
76H
77H
78H
79H
7AH
7BH
7CH
7DH
7EH
7FH
L21E07
L21E17
SRCV11
HTRIG7
HTRIG10
SBLBN
CCEN1
RCV2S7
RCV2E7
0
TTXHS7
TTXHD7
0
TTXOVS7
TTXOVE7
TTXEVS7
TTXEVE7
FAL7
LAL7
TTX60
0
LINE12
LINE20
L21E06
L21E16
SRCV10
HTRIG6
HTRIG9
0
CCEN0
RCV2S6
RCV2E6
RCV2E10
TTXHS6
TTXHD6
0
TTXOVS6
TTXOVE6
TTXEVS6
TTXEVE6
FAL6
LAL6
LAL8
0
LINE11
LINE19
L21E05
L21E15
TRCV2
HTRIG5
HTRIG8
PHRES1
TTXEN
RCV2S5
RCV2E5
RCV2E9
TTXHS5
TTXHD5
0
TTXOVS5
TTXOVE5
TTXEVS5
TTXEVE5
FAL5
LAL5
0
0
LINE10
LINE18
L21E04
L21E14
ORCV1
HTRIG4
VTRIG4
PHRES0
SCCLN4
RCV2S4
RCV2E4
RCV2E8
TTXHS4
TTXHD4
0
TTXOVS4
TTXOVE4
TTXEVS4
TTXEVE4
FAL4
LAL4
FAL8
0
LINE9
LINE17
L21E03
L21E13
PRCV1
HTRIG3
VTRIG3
0
SCCLN3
RCV2S3
RCV2E3
0
TTXHS3
TTXHD3
0
TTXOVS3
TTXOVE3
TTXEVS3
TTXEVE3
FAL3
LAL3
TTXEVE8
0
LINE8
LINE16
L21E02
L21E12
CBLF
HTRIG2
VTRIG2
0
SCCLN2
RCV2S2
RCV2E2
RCV2S10
TTXHS2
TTXHD2
VS_S2
TTXOVS2
TTXOVE2
TTXEVS2
TTXEVE2
FAL2
LAL2
TTXOVE8
0
LINE7
LINE15
L21E01
L21E11
ORCV2
HTRIG1
VTRIG1
FLC1
SCCLN1
RCV2S1
RCV2E1
RCV2S9
TTXHS1
TTXHD1
VS_S1
TTXOVS1
TTXOVE1
TTXEVS1
TTXEVE1
FAL1
LAL1
TTXEVS8
0
LINE6
LINE14
L21E00
L21E10
PRCV2
HTRIG0
VTRIG0
FLC0
SCCLN0
RCV2S0
RCV2E0
RCV2S8
TTXHS0
TTXHD0
VS_S0
TTXOVS0
TTXOVE0
TTXEVS0
TTXEVE0
FAL0
LAL0
TTXOVS8
0
LINE5
LINE13
Note
1. All bits labelled ‘0’ are reserved. They must be programmed with logic 0.