SAA7120H Datasheet, PDF (19/36 Pages) NXP Semiconductors – Digital video encoder

Philips Semiconductors
Digital video encoder
Product specification
SAA7120H; SAA7121H
Table 29 Logic levels and function of FLC
DATA BYTE
FLC1
0
0
1
1
FLC0
0
1
0
1
DESCRIPTION
interlaced 312.5 lines/field at 50 Hz, 262.5 lines/field at 60 Hz; default after reset
non-interlaced 312 lines/field at 50 Hz, 262 lines/field at 60 Hz
non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz
non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz
Table 30 Subaddress 6FH
DATA BYTE
CCEN
TTXEN
SCCLN
LOGIC
LEVEL
−
0
1
−
DESCRIPTION
enables individual line 21 encoding; see Table 31
disables teletext insertion; default after reset
enables teletext insertion
selects the actual line, where closed caption or extended data are encoded;
line = (SCCLN + 4) for M-systems; line = (SCCLN + 1) for other systems
Table 31 Logic levels and function of CCEN
DATA BYTE
CCEN1
CCEN0
0
0
0
1
1
0
1
1
DESCRIPTION
line 21 encoding off; default after reset
enables encoding in field 1 (odd)
enables encoding in field 2 (even)
enables encoding in both fields
Table 32 Subaddresses 70H to 72H
DATA BYTE
DESCRIPTION
RCV2S
start of output signal on pin RCV2
values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed; first active pixel at analog outputs
(corresponding input pixel coinciding with RCV2) at RCV2S = 11AH (0FDH)
RCV2E
end of output signal on pin RCV2
values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed; last active pixel at analog outputs
(corresponding input pixel coinciding with RCV2) at RCV2E = 694H (687H)
Table 33 Subaddresses 73H and 74H
DATA BYTE
DESCRIPTION
TTXHS
start of signal on pin TTXRQ; see Fig.10
TTXHD
indicates the delay in clock cycles between rising edge of
TTXRQ output and valid data at pin TTX
REMARKS
PAL: TTXHS = 42H
NTSC: TTXHS = 54H
minimum value: TTXHD = 2
2002 Oct 11
19