TDA8002C Datasheet, PDF (10/28 Pages) NXP Semiconductors – IC card interface

Philips Semiconductors
IC card interface
Product specification
TDA8002C
Table 1 Clock circuitry definition
MODE
CLKSEL
HIGH
HIGH
HIGH
HIGH
HIGH
LOW⁽²⁾
LOW
LOW
LOW
LOW
HIGH
X⁽¹⁾
Notes
1. X = don’t care.
2. In low-power mode.
3. f_int = 32 kHz in low-power mode.
CLKDIV1
HIGH
LOW
LOW
HIGH
X⁽¹⁾
X⁽¹⁾
CLKDIV2
LOW
LOW
HIGH
HIGH
X⁽¹⁾
X⁽¹⁾
FREQUENCY OF FREQUENCY OF
CLK
CLKOUT
1_⁄2fint
1_⁄4fxtal
1_⁄2fxtal
STOP low
STROBE
STOP low
1_⁄2fint
f_xtal
f_xtal
f_xtal
f_xtal
1_{⁄2fint(3)}
I/O circuitry
The three I/O transceivers are identical. The state is HIGH
for all I/O pins (i.e. I/O, I/OUC, AUX1, AUX1UC, AUX2 and
AUX2UC). Pin I/O is referenced to V_CC and pin I/OUC to
V_DD, thus ensuring proper operation in the event that
V_CC ≠ V_DD.
The first side on which a falling edge is detected becomes
a master (input). An anti-latch circuitry first disables the
detection of the falling edge on the other side, which
becomes slave (output), see Fig.8.
After a delay time t_d (between 50 and 400 ns), the logic 0
present on the master side is transferred on the slave side.
When the input is back to HIGH level, a current booster is
turned on during the delay t_d on the output side and then
both sides are back to their idle state, ready to detect the
next logic 0 on any side.
In the event of a conflict, both lines may remain LOW until
the software enables the lines to be HIGH. The anti-latch
circuitry ensures that the lines do not remain LOW if both
sides return HIGH, regardless of the prior conditions.
The maximum frequency on the lines is approximately
200 kHz.
When CS is HIGH, I/OUC, AUX1UC and AUX2UC are
internally pulled-up to V_DD with 20 kΩ resistors. When
CS is LOW, I/OUC, AUX1UC and AUX2UC are
permanently HIGH (with integrated 100 kΩ pull-up
resistors connected to V_DD).
handbook, full pagewidth_I/O
I/OUC
td
1999 Oct 12
td
td
conflict
idle
MGD703
Fig.8 Master and slave signals.
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