PE3282A Datasheet, PDF (9/14 Pages) Peregrine Semiconductor Corp. – 1.1 GHz/510 MHz Dual Fractional-N PLL IC for Frequency Synthesis

1.1 GHz/510 MHz Dual PLL IC
Table 10. f_oLD Programming Truth Table
X = don’t care condition
f_oLD
Output State
Disabled (Note 1)
PLL1 Lock detect (Note 2) (LD1)
PLL2 Lock detect (Note 2) (LD2)
PLL1/PLL2 Lock detect (Note 2)
PLL1 Reference divider output (f_c1)
PLL2 Reference divider output (f_c2)
PLL1 Programmable divider output (f_p1)
PLL2 Programmable divider output (f_p2)
Serial data out
Reserved
Reserved
Counter reset (Note 3)
C ₁₄
(PLL1 f_o)
0
0
0
0
1
0
1
0
1
1
1
1
C ₁₃
(PLL1 LD)
0
1
0
1
X
X
X
X
0
0
1
1
C ₂₄
(PLL2 f_o)
0
0
0
0
0
1
0
1
1
1
1
1
C ₂₃
(PLL2 LD)
0
0
1
1
0
0
1
1
0
1
0
1
Note 1: When the f_oLD is disabled the output is a CMOS LOW.
Note 2: Lock detect indicates when the VCO frequency is in “lock”. When PLL1 is in lock and PLL1 lock detect is selected, the f_oLD pin
will be HIGH, with narrow pulses LOW. When PLL2 is in lock and PLL2 lock detect is selected, the f_oLD pin will be HIGH, with narrow
pulses LOW. When PLL1/PLL2 lock detect is selected the f_oLD pin will be HIGH with narrow pulses LOW, only when both PLL1 and PLL2
are in lock.
Note 3: The counter reset state when activated resets all counters. Upon removal of the reset, counters M, A, and F resume counting in
close alignment with the R counter (the maximum error is one prescaler cycle). The reset bits can be activated to allow smooth
acquisition upon powering up.
Document 70/0002~07B
Peregrine Semiconductor Corporation^®
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