PE3282A Datasheet, PDF(10/14 Page) Peregrine Semiconductor Corp. – 1.1 GHz/510 MHz Dual Fractional-N PLL IC for Frequency Synthesis

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PE3282A Datasheet, PDF (10/14 Pages) Peregrine Semiconductor Corp. – 1.1 GHz/510 MHz Dual Fractional-N PLL IC for Frequency Synthesis

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PE3282A

Phase Comparator Characteristics

PLL1 has the timing relationships shown below for fc1, fp1, LD1, UP1, and DOWN1. When C11 = HIGH, UP1 directs the

internal PLL1 charge pump to source current and DOWN1 directs the PLL1 internal charge pump to sink current. If C11 =

LOW, UP1 and DOWN1 are interchanged.

PLL2 has the timing relationships shown below for fc2, fp2, LD2, UP2, and DOWN2. When C21 = HIGH, UP2 directs the

internal PLL2 charge pump to source current and DOWN2 directs the PLL2 internal charge pump to sink current. If C21 =

LOW, UP2 and DOWN2 are interchanged.

Figure 6. Phase Comparator Timing Diagram

fc1(2)

(Note 1)

fp1(2)

(Note 1)

LD1(2)

(Note 1)

UP1(2)

DOWN1(2)

fc leads fp

fc = fp

fc lags fp

Note 1: fc1(2), fp1(2), and LD1(2) are accessible via the foLD pin per programming in Table 10.

Document 70/0002~07B

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