PE3282A Datasheet, PDF (5/14 Pages) Peregrine Semiconductor Corp. – 1.1 GHz/510 MHz Dual Fractional-N PLL IC for Frequency Synthesis

1.1 GHz/510 MHz Dual PLL IC
Table 6. AC Characteristics
V_DD = 3.0 V, –40° C < T_A < 85° C, unless specified
Symbol
Parameter
Serial Control Interface (see Figure 3)
Conditions
Min
f_Clock
Serial data clock frequency
t_ClockH
Serial clock HIGH time
50
t_ClockL
Serial clock LOW time
50
t_DSU
Data set-up time to Clock rising edge
50
t_DHLD
Data hold time after Clock rising edge
10
t_LEW
LE pulse width
50
t_CLE
Clock falling edge to LE rising edge
50
t_LEC
LE falling edge to Clock rising edge
50
t_{Data Out}
Data Out delay after Clock falling edge
(f_oLD pin)
C_L = 50 pf
Main Divider (Including Prescaler)
f_in1
Operating frequency
f_in2
Operating frequency
P_fin1
Input level range
P_fin2
Input level range
f_c
Comparison frequency
Reference Divider
100
45
External AC coupling
–10
External AC coupling
–10
f_r
Operating frequency
V_fr
Input sensitivity
External AC coupling
0.5
(Note 1)
Note 1: CMOS logic levels may be used if DC coupled.
Max
Unit
10
MHz
ns
ns
ns
ns
ns
ns
ns
90
ns
1,100
510
5
5
10
50
MHz
MHz
dBm
dBm
MHz
MHz
V_P-P
Document 70/0002~07B
Peregrine Semiconductor Corporation^®
5