PE3282A Datasheet, PDF (2/14 Pages) Peregrine Semiconductor Corp. – 1.1 GHz/510 MHz Dual Fractional-N PLL IC for Frequency Synthesis

PE3282A
Figure 2. Pin Configuration TSSOP (JEDEC MO-153-AC)
Table 1. PE3282A Pin Description
V_{DD 1}
V_{DD 2}
CP1 3
Gnd 4
f_in1 ₅
f_in1 ₆
Gnd 7
f_r 8
Gnd 9
f_oLD 10
20 V_DD
19 V_DD
18 CP2
17 Gnd
16 f_in2
15 f_in2
14 Gnd
13 LE
12 Data
11 Clock
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
Pin Name
V_DD
V_DD
CP1
Gnd
f_in1
f_in1
Gnd
f_r
Gnd
f_oLD
Clock
Data
13
LE
14
Gnd
15
f_in2
16
f_in2
17
Gnd
18
CP2
19
V_DD
20
V_DD
Type
(Note 1)
(Note 1)
Output
Input
Input
Input
Output
Input
Input
Input
Input
Input
Output
(Note 1)
(Note 1)
Description
Power supply voltage input. Input may range from 2.7 V to 3.6 V. A bypass capacitor should be
placed as close as possible to this pin and be connected directly to the ground plane.
Same as pin 1.
Internal charge-pump output for PLL1. For connection to a loop filter for driving the input of
an external VCO.
Ground.
Prescaler input from the PLL1 (RF) VCO. 1.1 GHz max frequency.
1.1 GHz prescaler complementary input. A bypass capacitor should be placed as close as
possible to this pin and be connected directly to the ground plane. Capacitor is optional with
some loss of sensitivity.
Ground.
Reference frequency input.
Ground.
Multiplexed output of the PLL1 and PLL2 main counters or reference counters, Lock Detect
signals, and data out of the shift register. CMOS output (see Table 10, f_oLD Programming
Truth Table).
CMOS clock input. Serial data for the various counters is clocked in on the rising edge into the
21-bit shift register. A pull-down resistor is recommended.
Binary serial data input. CMOS input data entered MSB first. The two LSBs are the control bits.
A pull-down resistor is recommended.
Load Enable CMOS input. When LE is high, data word stored in the 21-bit serial shift register is
loaded into one of the four appropriate latches (as assigned by the control bits). A pull-down
resistor is recommended.
Ground.
510 MHz prescaler complementary input. A bypass capacitor should be placed as close as
possible to this pin and be connected directly to the ground plane. Capacitor is optional with
some loss of sensitivity.
Prescaler input from the PLL2 (IF) VCO. 510 MHz max frequency.
Ground.
Internal charge-pump output for PLL2. For connection to a loop filter for driving the input of
an external VCO.
Same as pin 1.
Same as pin 1.
Note 1: V_DD pins 1, 2, 19, and 20 are connected by diodes and must be supplied with the same voltage level.
2
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