PE3282A Datasheet, PDF(8/14 Page) Peregrine Semiconductor Corp. – 1.1 GHz/510 MHz Dual Fractional-N PLL IC for Frequency Synthesis

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PE3282A Datasheet, PDF (8/14 Pages) Peregrine Semiconductor Corp. – 1.1 GHz/510 MHz Dual Fractional-N PLL IC for Frequency Synthesis

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PE3282A

Programmable Divide Values

(R1, R2, F1, F2, A1, A2, M1, M2)

Data is clocked into the 21-bit shift register, MSB first.

When LE is asserted HIGH, data is latched into the

registers addressed by the last two bits shifted into the

21-bit shift register, according to Table 7. For example, to

program the PLL1 (RF) swallow counter, A1, the last two

bits shifted into the register (S0 , S1) would be (1, 1). The 5-

bit A1 counter would then be programmed according to

Table 8. For normal operation, S16 of address (0, 0) (the

Test bit) must be programmed to 0 even if PLL2 (IF) is not

used.

Table 8. PE3282A Counter Programming Example

Divide MSB

Value

LSB Address

S11 S10 S9

A14 A13 A12 A11 A10 1

â¢

31 1

Programmable Modes

Several modes of operation can be programmed with bits C10 - C14 and C20 - C24 , including the phase detector polarity,

charge pump high impedance, output of the foLD pin and power-down modes. The truth table for the programmable

modes is shown in Table 9. The truth table for the foLD output is shown in Table 10.

Table 9. PE3282A Programmable Modes

S15

S14

S13

S12

S11

S1 S0

C24

see

Table 10

C23

see

Table 10

C22

0 = PLL2 CP normal

1 = PLL2 CP High Z

C21 (Note 2)

0 = PLL2 Phase Detector inverted

1 = PLL2 Phase Detector normal

C20 (Note 1)

0 = PLL2 on

1 = PLL2 off

C14

see

Table 10

C13

see

Table 10

C12

0 = PLL1 CP normal

1 = PLL1 CP High Z

C11 (Note 2)

0 = PLL1 Phase Detector inverted

1 = PLL1 Phase Detector normal

C10 (Note 1)

0 = PLL1 on

1 = PLL1 off

Note 1: The PLL1 power-down mode disables all of PLL1âs components except the R1 counter and the reference frequency input buffer,

with CP1 (pin 3) and fin1 (pin 5) becoming high impedance. The power down of PLL2 has similar results with CP2 (pin 18) and fin2 (pin

16) becoming high impedance. Power down of both PLL1 and PLL2 further disables counters R1 and R2, the reference frequency input,

and the foLD output, causing fr (pin 8) and foLD (pin 10) to become high impedance. The Serial Control Interface remains active at all

times.

Note 2: The C11 and C21 bits should be set according to the voltage versus frequency slope of the VCO as shown in Figure 4. This

relationship presumes the use of a passive loop filter. If an inverting active loop filter is used the relationship is also inverted.

â¢ When VCO1 (RF) slope is positive like (1), C11 should be set HIGH.

â¢ When VCO1 (RF) slope is negative like (2), C11 should be set LOW.

â¢ When VCO2 (IF) slope is positive like (1), C21 should be set HIGH.

â¢ When VCO2 (IF) slope is negative like (2), C21 should be set LOW.

Figure 5. VCO Characteristics

VCO

Output

Frequency

(1) Positive Slope VCO

VCO Input Voltage

(2) Negative Slope VCO

Document 70/0002~07B

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