PE3282A Datasheet, PDF (11/14 Pages) Peregrine Semiconductor Corp. – 1.1 GHz/510 MHz Dual Fractional-N PLL IC for Frequency Synthesis

1.1 GHz/510 MHz Dual PLL IC
Figure 7. Typical Application Example
V_DD V_DD
V_DD V_DD
.01 µF ^{220 pF}
220 pF _{.01 µF .01 µF} 220 pF
220 pF
.01 µF
220 pF
PLL1 (RF)
OUT
VCO
(Note 1)
R2
C2 C1
R1
(Note 2)
220 pF
Reference
Input
f_oLD
Output
1000 pF
(Note 3)
V_DD
V_DD
CP1
Gnd
f_in1
f_in1
Gnd
f_r
Gnd
f_oLD
V_DD
V_DD
CP2
Gnd
f_in2
f_in2
Gnd
LE
Data
Clock
R4
C3 C4
R3
(Note 2)
1000 pF
1000 pF
VCO
(Note 1)
PLL2 (IF)
OUT
51K
51K
51K
From
Controller
Table 11. PLL1 (RF)
Operating
Conditions
Loop Filter
Values (Note 4)
f_out = 948.075 MHz
f_ref = 14.4 MHz
f_comp = 800 kHz
Fractionality = 32
R2 = 30 k ohm
C2 =.0043 µF
C1 = 900 pF
Step Size = 25 kHz
ω_n = 3.0 kHz
Phase Margin = 45°
N = 1,185 + 3/32
(M = 37, A = 1, F = 3)
K_VCO = 13 MHz/V
Kpd = 70 µA/2 ¼ rad
Table 12. PLL2 (IF)
Operating
Conditions
Loop Filter
Values (Note 4)
f_out = 130.45 MHz
f_ref = 14.4 MHZ
f_comp = 800 kHz
Fractionality = 16
R4 = 7.1 k ohm
C4 =.027 µF
C3 =.0056 µF
Step Size = 50 kHz
ω_n = 2.0 kHz
Phase Margin = 45°
N = 163 + 1/16
(M = 10, A = 3, F = 2)
K_VCO = 5 MHz/V
Kpd = 70 µA/2 ¼ rad
Note 1: VCO output assumed to be AC coupled.
Note 2: R1 and R3 are chosen to set the input drive to pins f_in1 and f_in2. R1 and R3 also allow a larger proportion of the VCO output to be
delivered to the load and attenuate reflected energy from the PLL inputs.
Note 3: The f_r input may be DC coupled if driven by an appropriate CMOS level signal. A 50 ohm terminating resistor can be used when
driving the f_r pin from an external 50 ohm signal source.
Note 4: The unity gain bandwidth is recommended to be less than or equal to 10 percent of the step size.
Document 70/0002~07B
Peregrine Semiconductor Corporation^®
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