PE3282A Datasheet, PDF (6/14 Pages) Peregrine Semiconductor Corp. – 1.1 GHz/510 MHz Dual Fractional-N PLL IC for Frequency Synthesis

PE3282A
Functional Description
The Functional Block Diagram in Figure 2 shows a 21-
bit serial control register, a multiplexed output, and PLL
sections PLL1 and PLL2. Each PLL contains a fractional-N
main counter chain, a reference counter, a phase
detector, and an internal charge pump with on-chip
fractional spur compensation. Each fractional-N main
counter chain includes an internal dual modulus
prescaler, supporting counters and a fractional
accumulator.
Serial input data is clocked on the rising edge of Clock,
MSB first. The last two bits are the address bits that
determine the register address. Data is transferred into
the counters as shown in Table 7, PE3282A Register Set. If
the f_oLD pin is configured as data out, then the contents
of shift register bit S₂₀ are clocked on the falling edge of
Clock onto the f_oLD pin. This feature allows the PE3282A
and compatible devices to be connected in a daisy-chain
configuration.
The PLL1 (RF) VCO frequency f_in1 is related to the
reference frequency f_r by the following equation:
f_in1 = [(32 x M₁) + A1 + (F₁/32)] x (f_r/R₁)
(1) Note that A₁ must be less than M₁. Also, f_in1 must be
greater than or equal to 1024 x (f_r/R₁) to obtain
contiguous channels.
The PLL2 (IF) VCO frequency f_in2 is related to the reference
frequency f_r by the following equation:
f_in2 = [(16 x M₂) + A2 + (F₂/32)] x (f_r/R₂)
(2) Note that A₂ must be less than M₂. Also, f_in2 must be
greater than or equal to 256 x (f_r/R₂) to obtain
contiguous channels.
F₁ sets PLL1 fractionality. If F₁ is an even number,
PE3282A automatically reduces the fraction. For
example, if F₁ = 12, then the fraction 12/32 is
automatically reduced to 3/8. In this way, fractional
denominators of 2, 4, 8, 16 and 32 are available. F₂ sets
the fractionality for PLL2 in the same manner.
Figure 3. PE3282A Functional Block Diagram
PLL1 (RF)
f_in1
f_in1
f_r
Clock
Data
LE
PLL2 (IF)
f_in2
f_in2
Prescaler
32/33
A₁
5
A₁ Counter
0 ð A₁ ð 31
M₁
9
M₁ Counter
3 ð M₁ ð 511
R₁ Counter
3 ð R₁ ð 511
R₁
9
Serial Control Interface
R₂
9
R₂ Counter
3 ð R₂ ð 511
Prescaler
16/17
M₂ Counter
3 ð M₂ ð 511
M₂
9
A₂ Counter
0 ð A₂ ð 15
A₂
4
Prescaler
Control Logic
F₁
5
F₁ Counter
0 ð F₁ ð 31
Phase
Detector
C₁₁
C₂₁
Phase
Detector
F₂ Counter
0 ð F₂ ð 31
F₂
5
Prescaler
Control Logic
Fractional
Compensation
Charge
Pump
C₁₂
f_oLD
Data Out
Multiplexer
C₂₂
Charge
Pump
CP1
CC₁₁₃₄
f_oLD
CC₂₂₄₃
CP2
Fractional
Compensation
6
Document 70/0002~07B