SAA1305T Datasheet, PDF (9/32 Pages) Panasonic Semiconductor – On/off logic IC

Philips Semiconductors
On/off logic IC
Product specification
SAA1305T
Watchdog timer
An internal Watchdog timer is active after each reset pulse
output and can be triggered via pin WD. In the event of a
not specified pulse, a delayed or missing trigger pulse, a
reset on pin RP will be the immediate reaction.
After the HIGH-to-LOW transition of the reset pulse output,
the first transition change within 500 ms on pin WD will be
detected as the first trigger from the microcontroller. The
timing diagram for the Watchdog timer trigger signal is
shown in Fig.5.
handbook, halfpage
RP
WD
(1)
(2)
(3)
MGR220
(1) In the event of a not specified, a delayed or missing trigger signal, a reset on pin RP will be the immediate reaction.
(2) The maximum time until signal change for first Watchdog timer is 500 ms.
(3) The time until next signal change is minimum 200 ms and maximum 300 ms.
Fig.5 Watchdog timer trigger timing.
Oscillators
Two oscillator types are built-in, a RC oscillator (designed
for 32.768 kHz) and a crystal oscillator (32.768 kHz), both
with separate pins. For a proper device function an
oscillator control circuit is integrated. This circuit
supervises the oscillator function and creates a reset and
oscillator restart in the event of an oscillator failure.
In the event of an oscillator fault, the event will be indicated
after a restart via the status register bit 5. During the
oscillator failure phase some outputs remain at a defined
level as shown in Table 3.
The RC oscillator accuracy is 5%.
When operating with the RC oscillator, pin XTAL2 must be
connected to V_DD or V_SS to minimize the quiescent
current. When operating with the crystal oscillator
pin OSC2 must be connected to V_SS or V_DD.
V_L timer
A built-in timer, which can be started with a HIGH-to-LOW
transition on pin TS, triggers, after 250 ms, pins RP
and CHI and sets pin ON/OFF. The V_L timer starts only
once after a valid start condition. Default state after a
Power-on reset is not active. A V_L timer start resets the
Watchdog timer. During run time of the V_L timer is
ON/OFF = LOW, CHI = 3-state and the Watchdog timer is
disabled.
Pin TS is only active during the run mode. During run time
of the V_L timer the IC remains in the wait mode. Only a
HIGH-level signal on input D0 can stop the V_L timer in the
same way as after 250 ms. In the event of an oscillator
fault the IC also enters the run mode but without an
influence on the status register bit 2. During the wait mode
an influence of the status register via other sources (e.g.
timer and inputs) is possible, but a transition from wait
mode to run mode is only possible as described above.
2004 Jan 15
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