SAA1305T Datasheet, PDF (15/32 Pages) Panasonic Semiconductor – On/off logic IC

Philips Semiconductors
On/off logic IC
Product specification
SAA1305T
Table 14 Definition of the watch and alarm register bits (write mode); notes 1, 2 and 3
ADDRESS (HEX)
2
3
4
5
6
7
DATA BITS
4 to 0
5 to 0
5 to 0
4 to 0
5 to 0
5 to 0
DESCRIPTION
hours of alarm
minutes of alarm
seconds of alarm
hours of watch
minutes of watch
seconds of watch
VALUES
0 to 31
0 to 63
0 to 63
0 to 23
0 to 59
0 to 59
DEFAULT
31
63
63
0
0
0
Notes
1. The alarm is disabled by writing a time larger than 24:00:00. With the default values the alarm function is disabled.
The alarm is also disabled if hours >23 or minutes >59 or seconds >59.
2. There are several attention points if a senseless time is written to the alarm register, for example:
a) Write 25 to address 2; data bits 4 to 0 = 25 ⇒ hours = 25 (alarm disabled).
b) Write 70 to address 3; data bits 5 to 0 = 6 ⇒ minutes = 6.
c) Write 81 to address 4; data bits 5 to 0 = 17 ⇒ seconds = 17.
3. There are several attention points if a senseless time is written to the watch register, for example:
a) Write 25 to address 5; data bits 4 to 0 = 25 ⇒ hours = 23 (limited).
b) Write 70 to address 6; data bits 5 to 0 = 6 ⇒ minutes = 6.
c) Write 81 to address 7; data bits 5 to 0 = 17 ⇒ seconds = 17.
Table 15 Definition of the impedance register bits
BIT
DESCRIPTION
7
no function
6
no function
5
no function
4
no function
3
no function
2
enable or disable bit for the impedance detection
0 = inactive (¹â„₂V_DD detection without influence on the status register)
1 = active (¹â„₂V_DD detection with influence on the status register)
1
bits 1 and 0 are control bits for the impedance detection delay time; see Table 16
0
Table 16 Control bits for the impedance detection delay time
BIT 1
0
0
1
1
BIT 0
0
1
0
1
DELAY TIME
100 ms
250 ms
500 ms
1s
2004 Jan 15
15