SAA1305T Datasheet, PDF (13/32 Pages) Panasonic Semiconductor – On/off logic IC

Philips Semiconductors
On/off logic IC
Product specification
SAA1305T
Write mode operations
After a START condition the master sends a device select
code with the R/W bit reset to logic 0; see Fig.8. The IC
acknowledge this and waits for the address byte. After the
address the master sends the corresponding data, which
is acknowledged by the IC. It is possible to continue with
the data transfer, each byte is acknowledged by the IC.
The internal byte address counter is incremented after
each data transmission.
The transfer is terminated when the master generates a
STOP condition. In the event of a wrong address decoding
the IC sends a no acknowledge signal and ignores all
following data.
Figure 9 shows the sequence for write data mode. Both
alarm and watch registers consist of 3 bytes. The first byte
(2 and 5) is the most significant byte. The definitions of the
bits are given in Tables 8, 10, 14 and 15.
handbook, full pagewidth
acknowledge
acknowledge
acknowledge acknowledge
acknowledge
S DEVICE SELECT
ADDRESS
DATA 1
DATA N
P
START
R/W
condition
MGR223
STOP
condition
Fig.8 I²C-bus write mode sequence.
handbook, full pagewidth _START
DEVICE SELECT ADDRESS CONTROL LED
byte
0
1
ALARM WATCH IMPEDANCE
2, 3, 4 5, 6, 7
8
STOP
MGR224
2004 Jan 15
Fig.9 I²C-bus write data sequence.
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