SAA1305T Datasheet, PDF (7/32 Pages) Panasonic Semiconductor – On/off logic IC

Philips Semiconductors
On/off logic IC
Product specification
SAA1305T
Serial I/O
The hardware of the I²C-bus interface (slave) operates
with a maximum clock frequency of 400 kHz.
Inputs
Pins D0 to D7 are connected to latches (new register).
Each latch contains and stores the input change until the
read out via the I²C-bus (read out of new register).
A second register (old register, latches) contains the input
situation before a ‘reset pulse’ signal or HIGH-to-LOW
transition of pin CHI. After a level change on any of the
inputs D0 to D7 (content of new register into ‘old’ register),
pin CHI will indicate this event. Reading the ‘old’ register
has no influence on any latch content. Reading the new
register will shift the content into the old register. During
the I²C-bus read sequence of the new register the latch
content will be shifted into the corresponding old latch and
afterwards the new latches are enabled until the next
change on this input. The functions of the inputs D0 to D7
are shown in Table 1.
Due to the fact, that a ‘reset pulse’ signal or a ‘change
information’ signal are also possible via the Watchdog
timer, V_L timer, alarm timer, impedance detection,
oscillator fault or after a device reset, the information about
these different events is also available via corresponding
bits within the status register; see Table 5.
A status I²C-bus read sequence resets the status register
and pin CHI. Only after a change on any of the inputs
D0 to D7, an I²C-bus read sequence of the status register,
old register and new register is it necessary to reset
pin CHI. The inputs D4 to D7 are maskable via the
I²C-bus; see Table 8. All masked inputs (defined via the
control register) are blocked to trigger pins CHI and RP.
During the disable phase of the masked inputs the
corresponding bits within the old and new registers will be
continuously refreshed with the actual input level.
Table 1 Input logic levels and functions
INPUT
D7
D6
D5
D4
D3
D2
D1
D0
SCHMITT
TRIGGER INPUT
SPECIAL INPUT
X
−
X
−
X
−
−
X
−
X
−
X
X
−
X
−
MASKABLE
X
X
X
X
−
−
−
−
V_L TIMER
INTERRUPT
−
−
−
−
−
−
−
X
IMPEDANCE
DETECTION
−
−
−
−
−
−
X
−
2004 Jan 15
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