MN85571AC Datasheet, PDF (9/16 Pages) Panasonic Semiconductor – Single-Chip Audio/Video MPEG2 Encoder

MN85571AC
s Electrical Characteristics
1. Absolute Maximum Ratings
Item
Symbol
Rating
Unit
Supply voltage 1
3.3V-VDD
− 0.3 to +4.6
V
Supply voltage 2
1.8V-VDD
− 0.3 to +2.5
V
Supply voltage 3
AVDD
− 0.3 to +4.6
V
Input voltage
VI
− 0.3 to 3.3 V-VDD + 0.3 (Upper limit: 4.6)
V
Output voltage
VO
− 0.3 to 3.3 V-VDD + 0.3 (Upper limit: 4.6)
V
Average output current
IO
±24
mA
Power dissipation
PD
2.3 (4 layers)
W
Operating temperature
Topr
0 to +70
°C
Storage temperature
Tstg
−40 to +125
°C
Note) 1. The absolute maximum ratings are limit values for stresses applied to the chip so that the chip will not be destroyed.
Operation is not guaranteed within these ranges.
2. All of the 3.3 V VDD pins, 1.8 V VDD pins, and VSS pins must be connected externally to the 3.3 V power supply, 1.8 V
power supply, and ground, respectively.
3. Connect bypass capacitors (at least 0.1 µF) between the 3.3 V VDD and VSS pins, between the 1.8 V VDD and VSS pins,
and between the AVDD and VSS pins.
4. The power supply voltages must be applied in the following order: first apply the 3.3 V system level (3.3V-VDD, AVDD),
and then apply the 1.8 V system level (1.8V-VDD).
When removing power from this IC, first remove the 1.8 V system level (1.8V-VDD) and then remove the 3.3 V system level
(3.3V-VDD, AVDD).
2. Recommended Operating Conditions at VSS = 0 V, AVSS = 0 V
Item
Symbol
Conditions
Min Typ Max Unit
Supply voltage 1
3.3V-VDD
3.0 3.3 3.6 V
Supply voltage 2
1.8V-VDD
1.65 1.80 1.95 V
Supply voltage 3
Ambient temperature
System clock frequency
Video data input clock
frequency
Code data output clock
frequency ^*2
DMA transfer clock frequency
PCM master clock frequency
AVDD
T_a
SCLK
VCLK
RCLKI
DMACLK
PCKI
3.3V-VDD = 3.0 V to 3.6 V
AVDD = 3.0 V to 3.6 V
DUTY: 50%±10%
Jitter: ±50 ppm ^*1
3.3V-VDD = 3.0 V to 3.6 V
DUTY: 50%±10%
Jitter: ±50 ppm ^*1
3.3V-VDD = 3.0 V to 3.6 V
DUTY: 50%±10%
3.3V-VDD = 3.0 V to 3.6 V
DUTY: 50%±10%
3.3V-VDD = 3.0 V to 3.6 V
DUTY: 50%±10%
3.0 3.3 3.6 V
0  70 °C
  27.0 MHz
  27.0 MHz
  33.0 MHz
  33.0 MHz
  18.432 MHz
Note) _*1: When TS output is used, the PCR counter SCLK and VCLK jitter must be held within ±30 ppm as stipulated by the ISO/
IEC 13818-1 standard.
*2: ^{The value shown for RCLKI is the stipulated value for forward clock input standalone mode. The maximum value for}
reverse clock input standalone mode is 16 MHz.
SDD00023AEM
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