MN85571AC Datasheet, PDF (3/16 Pages) Panasonic Semiconductor – Single-Chip Audio/Video MPEG2 Encoder

MN85571AC
s Internal Resource Mapping
The MN85571AC has two types of internal resources that are accessed by the external host with different methods.
1) Direct addressing resources (registers only)
These resources are mainly used for controlling this device and indicating the internal state of the device. These
are 16-bit registers.
2) Indirect addressing resources (registers and memory)
These are memory and other resources that mainly consist of parameter setting registers used at initialization and
memory that holds microcode.
1. Direct addressing resources
These are accessed by specifying the address to the external pins HA[3:0].
Table 1 shows the address mapping for the direct addressing resources.
Table 1. Direct Addressing Register Mapping
HA[3 : 0] Register r/w
Function
%0000 CHIPCTL0 r/w Control signal register 0 (reset, mode, srisc en)
%0001
Reserved
%0010
CHIPST0 r Status register 0 (interrupt)
%0011
CHIPST1 r Status register 1 (mode, busy)
%0100
STMSK r/w Status report signal mask register
%0101
Reserved
%0110
INADR0 r/w Indirect access address register
%0111
Reserved
%1000
INDAT0 r/w Indirect access data register
%1001
Reserved
%1010
DIFACC r/w DIF access register
%1011
DIFPTR r/w DIF access address register
%1100
DIFDAT r/w DIF access data register
%1101
Reserved
%1110
DMAACC r DMA access register
%1111
Reserved
Note) 1. CHIPCTL0 is only reset by a hardware reset (setting the external pin NRST low).
2. Chip operation is not guaranteed after access to any of the reserved direct addressing registers.
3. The symbols r and w indicate read and write as seen from the external host.
The symbol r alone indicates a read-only register, and r/w indicates the both read and write are possible.
4. Accesses to registers other than CHIPCTL0 are invalid in the reset state (software reset).
All register accesses are invalid in the hardware reset state.
5. The CHIPCTL0, CHIPST0, CHIPST1, STMASK, INADR0, and DIFPTR registers can all be read in the hold, slave, and
run states.
SDD00023AEM
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